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Added RTLIL and Liberty syntax highlighting to manual

This commit is contained in:
Clifford Wolf 2013-07-25 14:00:16 +02:00
parent 88d0829d65
commit 36c39cbd04
3 changed files with 19 additions and 4 deletions
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6
manual/CHAPTER_Overview.tex
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@ -300,7 +300,7 @@ In this example there is no data path and therefore the RTLIL::Module generated
the frontend only contains a few RTLIL::Wire objects and an RTLIL::Process. the frontend only contains a few RTLIL::Wire objects and an RTLIL::Process.
The RTLIL::Process in ILANG syntax: The RTLIL::Process in ILANG syntax:
\begin{lstlisting}[numbers=left,frame=single] \begin{lstlisting}[numbers=left,frame=single,language=rtlil]
process $proc$ff_with_en_and_async_reset.v:4$1 process $proc$ff_with_en_and_async_reset.v:4$1
assign $0\q[0:0] \q assign $0\q[0:0] \q
switch \reset switch \reset
@ -364,7 +364,7 @@ One of the first actions performed on a design in RTLIL representation in most
synthesis scripts is identifying asynchronous resets. This is usually done using the {\tt proc\_arst} synthesis scripts is identifying asynchronous resets. This is usually done using the {\tt proc\_arst}
pass. This pass transforms the above example to the following RTLIL::Process: pass. This pass transforms the above example to the following RTLIL::Process:
\begin{lstlisting}[numbers=left,frame=single] \begin{lstlisting}[numbers=left,frame=single,language=rtlil]
process $proc$ff_with_en_and_async_reset.v:4$1 process $proc$ff_with_en_and_async_reset.v:4$1
assign $0\q[0:0] \q assign $0\q[0:0] \q
switch \enable switch \enable
@ -383,7 +383,7 @@ This pass has transformed the outer RTLIL::SwitchRule into a modified RTLIL::Syn
for the {\tt \textbackslash{}reset} signal. Further processing converts the RTLIL::Process for the {\tt \textbackslash{}reset} signal. Further processing converts the RTLIL::Process
e.g.~into a d-type flip-flop with asynchronous reset and a multiplexer for the enable signal: e.g.~into a d-type flip-flop with asynchronous reset and a multiplexer for the enable signal:
\begin{lstlisting}[numbers=left,frame=single] \begin{lstlisting}[numbers=left,frame=single,language=rtlil]
cell $adff $procdff$6 cell $adff $procdff$6
parameter \ARST_POLARITY 1'1 parameter \ARST_POLARITY 1'1
parameter \ARST_VALUE 1'0 parameter \ARST_VALUE 1'0

2
manual/CHAPTER_Verilog.tex
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@ -533,7 +533,7 @@ end
This is translated by the Verilog and AST frontends into the following RTLIL code (attributes, cell parameters This is translated by the Verilog and AST frontends into the following RTLIL code (attributes, cell parameters
and wire declarations not included): and wire declarations not included):
\begin{lstlisting}[numbers=left,frame=single] \begin{lstlisting}[numbers=left,frame=single,language=rtlil]
cell $logic_not $logic_not$<input>:4$2 cell $logic_not $logic_not$<input>:4$2
connect \A \in1 connect \A \in1
connect \Y $logic_not$<input>:4$2_Y connect \Y $logic_not$<input>:4$2_Y

15
manual/manual.tex
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@ -102,6 +102,21 @@ bookmarksopen=false%
\setlength{\parskip}{1.5ex plus 1ex minus 0.5ex} \setlength{\parskip}{1.5ex plus 1ex minus 0.5ex}
\setlength{\parindent}{0pt} \setlength{\parindent}{0pt}
\lstdefinelanguage{liberty}{
morecomment=[s]{/*}{*/},
morekeywords={library,cell,area,pin,direction,function,clocked_on,next_state,clock,ff},
morestring=[b]",
}
\lstdefinelanguage{rtlil}{
morecomment=[l]{//},
morecomment=[s]{/*}{*/},
morekeywords={module,attribute,parameter,wire,memory,auto,width,offset,size,input,output,inout,cell,connect,switch,case,assign,sync,low,high,posedge,negedge,edge,always,update,process,end},
morestring=[b]",
}
\begin{document} \begin{document}
\fancypagestyle{mypagestyle}{% \fancypagestyle{mypagestyle}{%