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Test dffs separetely

This commit is contained in:
Miodrag Milanovic 2019-10-04 09:28:18 +02:00
parent 487b38b124
commit 36af102801
2 changed files with 19 additions and 26 deletions
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22
tests/xilinx/dffs.v
View File

@ -13,25 +13,3 @@ module dffe
if ( en ) if ( en )
q <= d; q <= d;
endmodule endmodule
module top (
input clk,
input en,
input a,
output b,b1,
);
dff u_dff (
.clk (clk ),
.d (a ),
.q (b )
);
dffe u_ndffe (
.clk (clk ),
.en (en),
.d (a ),
.q (b1 )
);
endmodule

23
tests/xilinx/dffs.ys
View File

@ -1,10 +1,25 @@
read_verilog dffs.v read_verilog dffs.v
hierarchy -top top design -save read
proc proc
flatten hierarchy -top dff
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG select -assert-count 1 t:BUFG
select -assert-count 2 t:FDRE select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
proc
hierarchy -top dffe
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D