From 36af10280136f0fda7b743075ac52e48576abf26 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 09:28:18 +0200
Subject: [PATCH] Test dffs separetely

---
 tests/xilinx/dffs.v  | 22 ----------------------
 tests/xilinx/dffs.ys | 23 +++++++++++++++++++----
 2 files changed, 19 insertions(+), 26 deletions(-)

diff --git a/tests/xilinx/dffs.v b/tests/xilinx/dffs.v
index d97840c43..3418787c9 100644
--- a/tests/xilinx/dffs.v
+++ b/tests/xilinx/dffs.v
@@ -13,25 +13,3 @@ module dffe
 		if ( en )
 			q <= d;
 endmodule
-
-module top (
-input clk,
-input en,
-input a,
-output b,b1,
-);
-
-dff u_dff (
-        .clk (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-dffe u_ndffe (
-        .clk (clk ),
-        .en (en),
-        .d (a ),
-        .q (b1 )
-    );
-
-endmodule
diff --git a/tests/xilinx/dffs.ys b/tests/xilinx/dffs.ys
index 6a98994c0..2d48a816c 100644
--- a/tests/xilinx/dffs.ys
+++ b/tests/xilinx/dffs.ys
@@ -1,10 +1,25 @@
 read_verilog dffs.v
-hierarchy -top top
+design -save read
+
 proc
-flatten
+hierarchy -top dff
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
-select -assert-count 2 t:FDRE
+select -assert-count 1 t:FDRE
+
 select -assert-none t:BUFG t:FDRE %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top dffe
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:FDRE
+
+select -assert-none t:BUFG t:FDRE %% t:* %D
+