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Added help messages for opt_* passes

This commit is contained in:
Clifford Wolf 2013-03-01 08:58:55 +01:00
parent 1bc0f04789
commit 36954471a6
7 changed files with 127 additions and 11 deletions
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25
passes/opt/opt.cc
View File

@ -26,7 +26,30 @@
bool OPT_DID_SOMETHING; bool OPT_DID_SOMETHING;
struct OptPass : public Pass { struct OptPass : public Pass {
OptPass() : Pass("opt") { } OptPass() : Pass("opt", "perform simple optimizations") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" opt [selection]\n");
log("\n");
log("This pass calls all the other opt_* passes in a useful manner. This performs\n");
log("a series of trivial optimizations and cleanups. This pass executes the other\n");
log("passes in the following order:\n");
log("\n");
log(" opt_const\n");
log(" opt_share -nomux\n");
log("\n");
log(" do\n");
log(" opt_muxtree\n");
log(" opt_reduce\n");
log(" opt_share\n");
log(" opt_rmdff\n");
log(" opt_rmunused\n");
log(" opt_const\n");
log(" while [changed design]\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{ {
log_header("Executing OPT pass (performing simple optimizations).\n"); log_header("Executing OPT pass (performing simple optimizations).\n");

21
passes/opt/opt_const.cc
View File

@ -44,14 +44,18 @@ void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, st
did_something = true; did_something = true;
} }
void replace_const_cells(RTLIL::Module *module) void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module)
{ {
if (!design->selected(module))
return;
SigMap assign_map(module); SigMap assign_map(module);
std::vector<RTLIL::Cell*> cells; std::vector<RTLIL::Cell*> cells;
cells.reserve(module->cells.size()); cells.reserve(module->cells.size());
for (auto &cell_it : module->cells) for (auto &cell_it : module->cells)
cells.push_back(cell_it.second); if (design->selected(module, cell_it.second))
cells.push_back(cell_it.second);
for (auto cell : cells) for (auto cell : cells)
{ {
@ -249,7 +253,16 @@ void replace_const_cells(RTLIL::Module *module)
} }
struct OptConstPass : public Pass { struct OptConstPass : public Pass {
OptConstPass() : Pass("opt_const") { } OptConstPass() : Pass("opt_const", "perform const folding") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" opt_const [selection]\n");
log("\n");
log("This pass performs const folding on internal cell types with constant inputs.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{ {
log_header("Executing OPT_CONST pass (perform const folding).\n"); log_header("Executing OPT_CONST pass (perform const folding).\n");
@ -260,7 +273,7 @@ struct OptConstPass : public Pass {
for (auto &mod_it : design->modules) for (auto &mod_it : design->modules)
do { do {
did_something = false; did_something = false;
replace_const_cells(mod_it.second); replace_const_cells(design, mod_it.second);
} while (did_something); } while (did_something);
log_pop(); log_pop();

22
passes/opt/opt_muxtree.cc
View File

@ -396,7 +396,20 @@ struct OptMuxtreeWorker
}; };
struct OptMuxtreePass : public Pass { struct OptMuxtreePass : public Pass {
OptMuxtreePass() : Pass("opt_muxtree") { } OptMuxtreePass() : Pass("opt_muxtree", "eliminate dead trees in multiplexer trees") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" opt_muxtree [selection]\n");
log("\n");
log("This pass analyzes the control signals for the multiplexer trees in the design\n");
log("and identifies inputs that can never be active. In then removes this dead\n");
log("branches from the multiplexer trees.\n");
log("\n");
log("This pass only operates on completely selected modules without processes.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{ {
log_header("Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n"); log_header("Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n");
@ -404,8 +417,13 @@ struct OptMuxtreePass : public Pass {
int total_count = 0; int total_count = 0;
for (auto &mod_it : design->modules) { for (auto &mod_it : design->modules) {
if (!design->selected_whole_module(mod_it.first)) {
if (design->selected(mod_it.second))
log("Skipping module %s as it is only partially selected.\n", id2cstr(mod_it.second->name));
continue;
}
if (mod_it.second->processes.size() > 0) { if (mod_it.second->processes.size() > 0) {
log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str()); log("Skipping module %s as it contains processes.\n", id2cstr(mod_it.second->name));
} else { } else {
OptMuxtreeWorker worker(design, mod_it.second); OptMuxtreeWorker worker(design, mod_it.second);
total_count += worker.removed_count; total_count += worker.removed_count;

17
passes/opt/opt_reduce.cc
View File

@ -216,7 +216,22 @@ struct OptReduceWorker
}; };
struct OptReducePass : public Pass { struct OptReducePass : public Pass {
OptReducePass() : Pass("opt_reduce") { } OptReducePass() : Pass("opt_reduce", "simplify large MUXes and AND/OR gates") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" opt_reduce [selection]\n");
log("\n");
log("This pass performs two interlinked optimizations:\n");
log("\n");
log("1. it consolidates trees of large AND gates or OR gates and eliminates\n");
log("duplicated inputs.\n");
log("\n");
log("2. it identifies duplicated inputs to MUXes and replaces them with a single\n");
log("input with the original control signals OR'ed together.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{ {
log_header("Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n"); log_header("Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n");

17
passes/opt/opt_rmdff.cc
View File

@ -93,7 +93,17 @@ delete_dff:
} }
struct OptRmdffPass : public Pass { struct OptRmdffPass : public Pass {
OptRmdffPass() : Pass("opt_rmdff") { } OptRmdffPass() : Pass("opt_rmdff", "remove DFFs with constant inputs") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" opt_rmdff [selection]\n");
log("\n");
log("This pass identifies flip-flops with constant inputs and replaces them with\n");
log("a constant driver.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{ {
int total_count = 0; int total_count = 0;
@ -103,10 +113,15 @@ struct OptRmdffPass : public Pass {
for (auto &mod_it : design->modules) for (auto &mod_it : design->modules)
{ {
if (!design->selected(mod_it.second))
continue;
assign_map.set(mod_it.second); assign_map.set(mod_it.second);
std::vector<std::string> dff_list; std::vector<std::string> dff_list;
for (auto &it : mod_it.second->cells) { for (auto &it : mod_it.second->cells) {
if (!design->selected(mod_it.second, it.second))
continue;
if (it.second->type == "$_DFF_N_") dff_list.push_back(it.first); if (it.second->type == "$_DFF_N_") dff_list.push_back(it.first);
if (it.second->type == "$_DFF_P_") dff_list.push_back(it.first); if (it.second->type == "$_DFF_P_") dff_list.push_back(it.first);
if (it.second->type == "$_DFF_NN0_") dff_list.push_back(it.first); if (it.second->type == "$_DFF_NN0_") dff_list.push_back(it.first);

21
passes/opt/opt_rmunused.cc
View File

@ -221,7 +221,21 @@ static void rmunused_module(RTLIL::Module *module)
} }
struct OptRmUnusedPass : public Pass { struct OptRmUnusedPass : public Pass {
OptRmUnusedPass() : Pass("opt_rmunused") { } OptRmUnusedPass() : Pass("opt_rmunused", "remove unused cells and wires") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" opt_rmunused [selection]\n");
log("\n");
log("This pass identifies wires and cells that are unused and removes them. Other\n");
log("often remove cells but leave the wires in the design or reconnect the wires\n");
log("but leave the old cells in the design. This pass can be used to clean up after\n");
log("the passes that do the actual work.\n");
log("\n");
log("This pass only operates on completely selected modules without processes.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{ {
log_header("Executing OPT_RMUNUSED pass (remove unused cells and wires).\n"); log_header("Executing OPT_RMUNUSED pass (remove unused cells and wires).\n");
@ -235,6 +249,11 @@ struct OptRmUnusedPass : public Pass {
ct.setup_stdcells_mem(); ct.setup_stdcells_mem();
for (auto &mod_it : design->modules) { for (auto &mod_it : design->modules) {
if (!design->selected_whole_module(mod_it.first)) {
if (design->selected(mod_it.second))
log("Skipping module %s as it is only partially selected.\n", id2cstr(mod_it.second->name));
continue;
}
if (mod_it.second->processes.size() > 0) { if (mod_it.second->processes.size() > 0) {
log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str()); log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
} else { } else {

15
passes/opt/opt_share.cc
View File

@ -218,7 +218,20 @@ struct OptShareWorker
}; };
struct OptSharePass : public Pass { struct OptSharePass : public Pass {
OptSharePass() : Pass("opt_share") { } OptSharePass() : Pass("opt_share", "consolidate identical cells") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" opt_share [-nomux] [selection]\n");
log("\n");
log("This pass identifies cells with identical type and input signals. Such cells\n");
log("are then merged to one cell.\n");
log("\n");
log(" -nomux\n");
log(" Do not merge MUX cells.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{ {
log_header("Executing OPT_SHARE pass (detect identical cells).\n"); log_header("Executing OPT_SHARE pass (detect identical cells).\n");