mirror of https://github.com/YosysHQ/yosys.git
Fixed bug where counter extraction on non-GreenPAK devices incorrectly handled parallel counter output
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c8f2f082c6
commit
367d6b2194
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@ -281,44 +281,34 @@ int counter_tryextract(
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max_loads = 3;
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max_loads = 3;
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if(cnout_loads.size() > max_loads)
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if(cnout_loads.size() > max_loads)
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{
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{
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//If we specified a limited set of cells for parallel output, check that we only drive them
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for(auto c : cnout_loads)
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if(!parallel_cells.empty())
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{
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{
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for(auto c : cnout_loads)
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if(c == underflow_inv)
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{
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continue;
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if(c == underflow_inv)
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if(c == cell)
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continue;
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continue;
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if(c == cell)
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if(c == muxload)
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continue;
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continue;
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if(c == muxload)
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continue;
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//If we specified a limited set of cells for parallel output, check that we only drive them
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if(!parallel_cells.empty())
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{
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//Make sure we're in the whitelist
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//Make sure we're in the whitelist
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if( parallel_cells.find(c->type) == parallel_cells.end())
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if( parallel_cells.find(c->type) == parallel_cells.end())
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return 17;
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return 17;
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}
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//Figure out what port(s) are driven by it
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//Figure out what port(s) are driven by it
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//TODO: this can probably be done more efficiently w/o multiple iterations over our whole net?
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//TODO: this can probably be done more efficiently w/o multiple iterations over our whole net?
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RTLIL::IdString portname;
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for(auto b : qport)
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for(auto b : qport)
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{
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pool<ModIndex::PortInfo> ports = index.query_ports(b);
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for(auto x : ports)
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{
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{
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pool<ModIndex::PortInfo> ports = index.query_ports(b);
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if(x.cell != c)
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for(auto x : ports)
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continue;
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{
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extract.pouts.insert(ModIndex::PortInfo(c, x.port, 0));
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if(x.cell != c)
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continue;
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if(portname == "")
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portname = x.port;
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//somehow our counter output is going to multiple ports
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//this makes no sense, don't allow inference
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else if(portname != x.port)
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return 17;
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}
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}
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}
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//Save the other loads
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extract.pouts.insert(ModIndex::PortInfo(c, portname, 0));
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}
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}
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}
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}
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}
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}
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@ -529,10 +519,15 @@ void counter_worker(
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string reset_type = "non-resettable";
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string reset_type = "non-resettable";
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if(extract.has_reset)
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if(extract.has_reset)
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{
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{
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if(extract.rst_inverted)
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reset_type = "negative";
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else
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reset_type = "positive";
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//TODO: support other kind of reset
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//TODO: support other kind of reset
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reset_type = "async resettable";
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reset_type += " async resettable";
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}
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}
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log(" Found %d-bit %s down counter %s (counting from %d) for register %s declared at %s\n",
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log(" Found %d-bit (%s) down counter %s (counting from %d) for register %s, declared at %s\n",
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extract.width,
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extract.width,
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reset_type.c_str(),
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reset_type.c_str(),
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countname.c_str(),
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countname.c_str(),
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