diff --git a/docs/source/yosys_internals/index.rst b/docs/source/yosys_internals/index.rst
index d349f6f1b..b04f13699 100644
--- a/docs/source/yosys_internals/index.rst
+++ b/docs/source/yosys_internals/index.rst
@@ -15,6 +15,8 @@ Yosys can synthesize a large subset of Verilog 2005 and has been tested with a
 wide range of real-world designs, including the `OpenRISC 1200 CPU`_, the
 `openMSP430 CPU`_, the `OpenCores I2C master`_, and the `k68 CPU`_.
 
+.. todo:: add RISC-V core example
+
 .. _OpenRISC 1200 CPU: https://github.com/openrisc/or1200
 
 .. _openMSP430 CPU: http://opencores.org/projects/openmsp430
@@ -23,13 +25,11 @@ wide range of real-world designs, including the `OpenRISC 1200 CPU`_, the
 
 .. _k68 CPU: http://opencores.org/projects/k68
 
-As of this writing, a Yosys VHDL frontend is in development.
-
-Yosys is written in C++ (using some features from the new C++11 standard). This
-chapter describes some of the fundamental Yosys data structures. For the sake of
-simplicity the C++ type names used in the Yosys implementation are used in this
-chapter, even though the chapter only explains the conceptual idea behind it and
-can be used as reference to implement a similar system in any language.
+Yosys is written in C++, targeting C++11 at minimum. This chapter describes some
+of the fundamental Yosys data structures. For the sake of simplicity the C++
+type names used in the Yosys implementation are used in this chapter, even
+though the chapter only explains the conceptual idea behind it and can be used
+as reference to implement a similar system in any language.
 
 .. toctree::
    :maxdepth: 3