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Revert "Different approach to timing" 

This reverts commit 41256f48a5.
This commit is contained in:
Eddie Hung 2019-09-19 18:33:38 -07:00
parent 41256f48a5
commit 362a803779
4 changed files with 407 additions and 197 deletions
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145
techlibs/xilinx/abc_map.v
View File

@ -299,60 +299,49 @@ __CELL__ #(
wire [47:0] iC; wire [47:0] iC;
wire [24:0] iD; wire [24:0] iD;
wire pAP, pBP, pCP, pDP, pADP, pMP, pPP; wire pA, pB, pC, pD, pAD, pM, pP;
wire pAPCOUT, pBPCOUT, pCPCOUT, pDPCOUT, pADPCOUT, pMPCOUT, pPPCOUT;
wire [47:0] oP, oPCOUT; wire [47:0] oP, oPCOUT;
// Disconnect the A-input if MREG is enabled, since // Disconnect the A-input if MREG is enabled, since
// combinatorial path is broken // combinatorial path is broken
if (AREG == 0 && MREG == 0 && PREG == 0) if (AREG == 0 && MREG == 0 && PREG == 0)
assign iA = A, pAP = 1'bx, pAPCOUT = 1'bx; assign iA = A, pA = 1'bx;
else else
\$__ABC_DSP48E1_MULT_AREG rA (.I(A), .O(iA), .P(pAP), .PCOUT(pAPCOUT)); \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
if (BREG == 0 && MREG == 0 && PREG == 0) if (BREG == 0 && MREG == 0 && PREG == 0)
assign iB = B, pBP = 1'bx, pBPCOUT = 1'bx; assign iB = B, pB = 1'bx;
else else
\$__ABC_DSP48E1_MULT_BREG rB (.I(B), .O(iB), .P(pBP), .PCOUT(pBPCOUT)); \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
if (CREG == 0 && PREG == 0) if (CREG == 0 && PREG == 0)
assign iC = C, pCP = 1'bx, pCPCOUT = 1'bx; assign iC = C, pC = 1'bx;
else else
\$__ABC_DSP48E1_MULT_CREG rC (.I(C), .O(iC), .P(pCP), .PCOUT(pCPCOUT)); \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
if (DREG == 0) if (DREG == 0)
assign iD = D; assign iD = D;
else if (techmap_guard) else if (techmap_guard)
$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
assign pDP = 1'bx, pDPCOUT = 1'bx; assign pD = 1'bx;
if (ADREG == 1 && techmap_guard) if (ADREG == 1 && techmap_guard)
$error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
assign pADP = 1'bx, pADPCOUT = 1'bx; assign pAD = 1'bx;
if (PREG == 0) begin if (PREG == 0) begin
assign pP = 1'bx;
if (MREG == 1) if (MREG == 1)
\$__ABC_DSP48E1_MULT_MREG rM (.P(pMP), .PCOUT(pMPCOUT)); \$__ABC_DSP48E1_REG rM (.Q(pM));
else else
assign pMP = 1'bx, pMPCOUT = 1'bx; assign pM = 1'bx;
assign pPP = 1'bx, pPPCOUT = 1'bx;
end end
else begin else begin
assign pMP = 1'bx, pMPCOUT = 1'bx; \$__ABC_DSP48E1_REG rP (.Q(pP));
\$__ABC_DSP48E1_MULT_PREG rP (.P(pPP), .PCOUT(pPPCOUT)); assign pM = 1'bx;
end end
if (MREG == 0 && PREG == 0) begin \$__ABC_DSP48E1_MULT_P_MUX muxP (
\$__ABC_DSP48E1_MUX muxP ( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
.Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(oP), .Pq(pPP), .O(P) );
); \$__ABC_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
\$__ABC_DSP48E1_MUX muxPCOUT ( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
.Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(oPCOUT), .Pq(pPPCOUT), .O(PCOUT) );
);
end
else begin
\$__ABC_DSP48E1_MUX muxP (
.Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(1'bx), .Pq(pPP), .O(P)
);
\$__ABC_DSP48E1_MUX muxPCOUT (
.Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(1'bx), .Pq(pPPCOUT), .O(PCOUT)
);
end
`DSP48E1_INST(\$__ABC_DSP48E1_MULT ) `DSP48E1_INST(\$__ABC_DSP48E1_MULT )
end end
@ -362,53 +351,46 @@ __CELL__ #(
wire [47:0] iC; wire [47:0] iC;
wire [24:0] iD; wire [24:0] iD;
wire pAP, pBP, pCP, pDP, pADP, pMP, pPP; wire pA, pB, pC, pD, pAD, pM, pP;
wire pAPCOUT, pBPCOUT, pCPCOUT, pDPCOUT, pADPCOUT, pMPCOUT, pPPCOUT;
wire [47:0] oP, oPCOUT; wire [47:0] oP, oPCOUT;
// Disconnect the A-input if MREG is enabled, since // Disconnect the A-input if MREG is enabled, since
// combinatorial path is broken // combinatorial path is broken
if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0) if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0)
assign iA = A, pAP = 1'bx, pAPCOUT = 1'bx; assign iA = A, pA = 1'bx;
else else
\$__ABC_DSP48E1_MULT_DPORT_AREG rA (.I(A), .O(iA), .P(pAP), .PCOUT(pAPCOUT)); \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
if (BREG == 0 && MREG == 0 && PREG == 0) if (BREG == 0 && MREG == 0 && PREG == 0)
assign iB = B, pBP = 1'bx, pBPCOUT = 1'bx; assign iB = B, pB = 1'bx;
else else
\$__ABC_DSP48E1_MULT_DPORT_BREG rB (.I(B), .O(iB), .P(pBP), .PCOUT(pBPCOUT)); \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
if (CREG == 0 && PREG == 0) if (CREG == 0 && PREG == 0)
assign iC = C, pCP = 1'bx, pCPCOUT = 1'bx; assign iC = C, pC = 1'bx;
else else
\$__ABC_DSP48E1_MULT_DPORT_CREG rC (.I(C), .O(iC), .P(pCP), .PCOUT(pCPCOUT)); \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
if (DREG == 0 && ADREG == 0) if (DREG == 0 && ADREG == 0)
assign iD = D, pDP = 1'bx, pDPCOUT = 1'bx; assign iD = D, pD = 1'bx;
else else
\$__ABC_DSP48E1_MULT_DPORT_DREG rD (.I(D), .O(iD), .P(pDP), .PCOUT(pDPCOUT)); \$__ABC_DSP48E1_REG rD (.I(D), .O(iD), .Q(pD));
if (PREG == 0) begin if (PREG == 0) begin
if (MREG == 1) begin if (MREG == 1)
assign pADP = 1'bx, pADPCOUT = 1'bx; \$__ABC_DSP48E1_REG rM (.Q(pM));
\$__ABC_DSP48E1_MULT_DPORT_MREG rM (.P(pMP), .PCOUT(pMPCOUT));
end
else begin else begin
assign pM = 1'bx;
if (ADREG == 1) if (ADREG == 1)
\$__ABC_DSP48E1_MULT_DPORT_ADPREG rAD (.P(pADP), .PCOUT(pADPCOUT)); \$__ABC_DSP48E1_REG rAD (.Q(pAD));
else else
assign pADP = 1'bx, pADPCOUT = 1'bx; assign pAD = 1'bx;
assign pMP = 1'bx, pMPCOUT = 1'bx;
end end
assign pPP = 1'bx, pPPCOUT = 1'bx;
end end
else begin else
assign pADP = 1'bx, pADPCOUT = 1'bx; \$__ABC_DSP48E1_REG rP (.Q(pP));
assign pMP = 1'bx, pMPCOUT = 1'bx;
\$__ABC_DSP48E1_MULT_DPORT_PREG rP (.P(pPP), .PCOUT(pPPCOUT));
end
\$__ABC_DSP48E1_MUX muxP ( \$__ABC_DSP48E1_MULT_DPORT_P_MUX muxP (
.Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(oP), .Pq(pPP), .O(P) .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
); );
\$__ABC_DSP48E1_MUX muxPCOUT ( \$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT (
.Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(oPCOUT), .Pq(pPPCOUT), .O(PCOUT) .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
); );
`DSP48E1_INST(\$__ABC_DSP48E1_MULT_DPORT ) `DSP48E1_INST(\$__ABC_DSP48E1_MULT_DPORT )
@ -419,43 +401,42 @@ __CELL__ #(
wire [47:0] iC; wire [47:0] iC;
wire [24:0] iD; wire [24:0] iD;
wire pAP, pBP, pCP, pDP, pADP, pMP, pPP; wire pA, pB, pC, pD, pAD, pM, pP;
wire pAPCOUT, pBPCOUT, pCPCOUT, pDPCOUT, pADPCOUT, pMPCOUT, pPPCOUT;
wire [47:0] oP, oPCOUT; wire [47:0] oP, oPCOUT;
// Disconnect the A-input if MREG is enabled, since // Disconnect the A-input if MREG is enabled, since
// combinatorial path is broken // combinatorial path is broken
if (AREG == 0 && PREG == 0) if (AREG == 0 && PREG == 0)
assign iA = A, pAP = 1'bx, pAPCOUT = 1'bx; assign iA = A, pA = 1'bx;
else else
\$__ABC_DSP48E1_AREG rA (.I(A), .O(iA), .P(pAP), .PCOUT(pAPCOUT)); \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
if (BREG == 0 && PREG == 0) if (BREG == 0 && PREG == 0)
assign iB = B, pBP = 1'bx, pBPCOUT = 1'bx; assign iB = B, pB = 1'bx;
else else
\$__ABC_DSP48E1_BREG rB (.I(B), .O(iB), .P(pB), .PCOUT(pBPCOUT)); \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
if (CREG == 0 && PREG == 0) if (CREG == 0 && PREG == 0)
assign iC = C, pCP = 1'bx, pCPCOUT = 1'bx; assign iC = C, pC = 1'bx;
else else
\$__ABC_DSP48E1_CREG rC (.I(C), .O(iC), .P(pC), .PCOUT(pCPCOUT)); \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
if (DREG == 1 && techmap_guard)
$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
assign iD = 25'bx, pDP = 1'bx, pDPCOUT = 1'bx;
if (ADREG == 1 && techmap_guard)
$error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
assign pADP = 1'bx, pADPCOUT = 1'bx;
if (MREG == 1 && techmap_guard) if (MREG == 1 && techmap_guard)
$error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\""); $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
assign pMP = 1'bx, pMPCOUT = 1'bx; assign pM = 1'bx;
if (DREG == 1 && techmap_guard)
$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
assign pD = 1'bx;
if (ADREG == 1 && techmap_guard)
$error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
assign pAD = 1'bx;
if (PREG == 1) if (PREG == 1)
\$__ABC_DSP48E1_PREG rP (.P(pPP), .P(pPCOUT)); \$__ABC_DSP48E1_REG rP (.Q(pP));
else else
assign pPP = 1'bx, pPPCOUT = 1'bx; assign pP = 1'bx;
\$__ABC_DSP48E1_MUX muxP ( \$__ABC_DSP48E1_P_MUX muxP (
.Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(oP), .Pq(pPP), .O(P) .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
); );
\$__ABC_DSP48E1_MUX muxPCOUT ( \$__ABC_DSP48E1_PCOUT_MUX muxPCOUT (
.Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(oPCOUT), .Pq(pPPCOUT), .O(PCOUT) .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
); );
`DSP48E1_INST(\$__ABC_DSP48E1 ) `DSP48E1_INST(\$__ABC_DSP48E1 )

105
techlibs/xilinx/abc_model.v
View File

@ -44,6 +44,48 @@ endmodule
module \$__ABC_LUT7 (input A, input [6:0] S, output Y); module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
endmodule endmodule
// Boxes used to represent the comb/seq behaviour of DSP48E1
// With abc_map.v responsible for disconnecting inputs to
// the combinatorial DSP48E1 model by a register (e.g.
// disconnecting A when AREG, MREG or PREG is enabled)
// this blackbox captures the existence of a replacement
// path between AREG/BREG/CREG/etc. and P/PCOUT.
// Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at
// the box at zero time, the combinatorial delay through
// these boxes thus represents the clock-to-q delay
// (arrival time) at P/PCOUT.
// Doing so should means that ABC is able to analyse the
// worst-case delay through to P, regardless of if it was
// through any combinatorial paths (e.g. B, below) or an
// internal register (A2REG).
// However, the true value of being as complete as this is
// questionable since if AREG=1 and BREG=0 (as below)
// then the worse-case path would very likely be through B
// and very unlikely to be through AREG.Q...?
//
// In graphical form:
//
// NEW "PI" >>---+
// for AREG.Q |
// |
// +---------+ | __
// A >>--X X-| | +--| \
// | DSP48E1 |P | |--->> P
// | AREG=1 |-------|__/
// B >>------| |
// +---------+
//
`define ABC_DSP48E1_MUX(__NAME__) """
module __NAME__ (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O);
endmodule
"""
(* abc_box_id=2100 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_P_MUX )
(* abc_box_id=2101 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_PCOUT_MUX )
(* abc_box_id=2102 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_P_MUX )
(* abc_box_id=2103 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX )
(* abc_box_id=2104 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_P_MUX )
(* abc_box_id=2105 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_PCOUT_MUX )
`define ABC_DSP48E1(__NAME__) """ `define ABC_DSP48E1(__NAME__) """
module \$__ABC_DSP48E1_MULT ( module \$__ABC_DSP48E1_MULT (
output [29:0] ACOUT, output [29:0] ACOUT,
@ -131,66 +173,3 @@ endmodule
(* abc_box_id=3000 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT ) (* abc_box_id=3000 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT )
(* abc_box_id=3001 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT_DPORT ) (* abc_box_id=3001 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT_DPORT )
(* abc_box_id=3002 *) `ABC_DSP48E1(\$__ABC_DSP48E1 ) (* abc_box_id=3002 *) `ABC_DSP48E1(\$__ABC_DSP48E1 )
// Modules used to model the comb/seq behaviour of DSP48E1
// With abc_map.v responsible for splicing the below modules
// into between the combinatorial DSP48E1 box (e.g. disconnecting
// A when AREG, MREG or PREG is enabled and splicing in the
// "$__ABC_DSP48E1_MULT_AREG" blackbox as "REG" in the diagram
// below) this acts to first disables the combinatorial path
// (as there is no connectivity through REG), and secondly,
// since this is blackbox a new PI will be introduced, one which
// will have the relevant arrival time (corresponding to delay from
// AREG to P) attached.
// Note: Since these "$__ABC_DSP48E1*_*REG" modules are of a
// sequential nature, they are not passed as a box to ABC./
//
// On the other hand, the "$__ABC_DSP48E1_MUX" is a combinatorial
// blackbox that is passed to ABC, with zero delay.
//
// Doing so should means that ABC is able to analyse the
// worst-case delay through to P, regardless of if it was
// through any combinatorial paths (e.g. B, below) or an
// internal register (A2REG).
// However, the true value of being as complete as this is
// questionable since if AREG=1 and BREG=0 (as below)
// then the worse-case path would very likely be through B
// and very unlikely to be through AREG.Q...?
//
// In graphical form:
//
// +-----+
// +-------| REG |-----+
// | +-----+ |
// | |
// | +---------+ | __
// A >>-+X X-| | +--| \
// | DSP48E1 |P | M |--->> P
// | AREG=1 |-------|__/
// B >>------| |
// +---------+
//
(* abc_box_id=2100 *)
module \$__ABC_DSP48E1_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O);
endmodule
module $__ABC_DSP48E1_MULT_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=2952 *) output P, (* abc_arrival=3098 *) output PCOUT); endmodule
module $__ABC_DSP48E1_MULT_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=2813 *) output P, (* abc_arrival=2960 *) output PCOUT); endmodule
module $__ABC_DSP48E1_MULT_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule
module $__ABC_DSP48E1_MULT_MREG (input [47:0] I, output [47:0] O, (* abc_arrival=1671 *) output P, (* abc_arrival=1819 *) output PCOUT); endmodule
module $__ABC_DSP48E1_MULT_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule
module $__ABC_DSP48E1_MULT_DPORT_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=3935 *) output P, (* abc_arrival=4083 *) output PCOUT); endmodule
module $__ABC_DSP48E1_MULT_DPORT_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=2813 *) output P, (* abc_arrival=2960 *) output PCOUT); endmodule
module $__ABC_DSP48E1_MULT_DPORT_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule
module $__ABC_DSP48E1_MULT_DPORT_DREG (input [47:0] I, output [47:0] O, (* abc_arrival=3908 *) output P, (* abc_arrival=4056 *) output PCOUT); endmodule
module $__ABC_DSP48E1_MULT_DPORT_ADREG (input [47:0] I, output [47:0] O, (* abc_arrival=2958 *) output P, (* abc_arrival=2859 *) output PCOUT); endmodule
module $__ABC_DSP48E1_MULT_DPORT_MREG (input [47:0] I, output [47:0] O, (* abc_arrival=1671 *) output P, (* abc_arrival=1819 *) output PCOUT); endmodule
module $__ABC_DSP48E1_MULT_DPORT_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule
module $__ABC_DSP48E1_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=1632 *) output P, (* abc_arrival=1780 *) output PCOUT); endmodule
module $__ABC_DSP48E1_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=1616 *) output P, (* abc_arrival=1765 *) output PCOUT); endmodule
module $__ABC_DSP48E1_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule
module $__ABC_DSP48E1_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule

4
techlibs/xilinx/abc_unmap.v
View File

@ -27,10 +27,10 @@ module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
assign Y = A; assign Y = A;
endmodule endmodule
(* techmap_celltype = "$__ABC_DSP48E1_MULT_AREG $__ABC_DSP48E1_MULT_BREG $__ABC_DSP48E1_MULT_CREG $__ABC_DSP48E1_MULT_MREG $__ABC_DSP48E1_MULT_PREG $__ABC_DSP48E1_MULT_DPORT_AREG $__ABC_DSP48E1_MULT_DPORT_BREG $__ABC_DSP48E1_MULT_DPORT_CREG $__ABC_DSP48E1_MULT_DPORT_DREG $__ABC_DSP48E1_MULT_DPORT_ADREG $__ABC_DSP48E1_MULT_DPORT_MREG $__ABC_DSP48E1_MULT_DPORT_PREG " *) module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output Q);
module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output P, PCOUT);
assign O = I; assign O = I;
endmodule endmodule
(* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC_DSP48E1_P_MUX $__ABC_DSP48E1_PCOUT_MUX" *)
module \$__ABC_DSP48E1_MUX ( module \$__ABC_DSP48E1_MUX (
input Aq, Bq, Cq, Dq, ADq, Mq, input Aq, Bq, Cq, Dq, ADq, Mq,
input [47:0] P, input [47:0] P,

350
techlibs/xilinx/abc_xc7.box
View File

@ -70,56 +70,306 @@ $__ABC_LUT7 2001 0 8 1
# the mux at zero time, the combinatorial delay through # the mux at zero time, the combinatorial delay through
# these muxes thus represents the clock-to-q delay at # these muxes thus represents the clock-to-q delay at
# P/PCOUT. # P/PCOUT.
$__ABC_DSP48E1_MUX 2100 0 55 48 $__ABC_DSP48E1_MULT_P_MUX 2100 0 55 48
#A AD B C D M P Pq # A AD B C D M P Pq
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$__ABC_DSP48E1_MULT 3000 0 263 154 $__ABC_DSP48E1_MULT 3000 0 263 154
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