riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed typos in verilog_defaults help message

This commit is contained in:
Clifford Wolf 2016-03-10 11:14:51 +01:00
parent d117893007
commit 35a6ad4cc1
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
frontends/verilog/verilog_frontend.cc
View File

@ -362,13 +362,13 @@ struct VerilogDefaults : public Pass {
log("Add the specified options to the list of default options to read_verilog.\n"); log("Add the specified options to the list of default options to read_verilog.\n");
log("\n"); log("\n");
log("\n"); log("\n");
log(" verilog_defaults -clear"); log(" verilog_defaults -clear\n");
log("\n"); log("\n");
log("Clear the list of Verilog default options.\n"); log("Clear the list of Verilog default options.\n");
log("\n"); log("\n");
log("\n"); log("\n");
log(" verilog_defaults -push"); log(" verilog_defaults -push\n");
log(" verilog_defaults -pop"); log(" verilog_defaults -pop\n");
log("\n"); log("\n");
log("Push or pop the list of default options to a stack. Note that -push does\n"); log("Push or pop the list of default options to a stack. Note that -push does\n");
log("not imply -clear.\n"); log("not imply -clear.\n");