diff --git a/docs/source/code_examples/fifo/fifo.out b/docs/source/code_examples/fifo/fifo.out
index 85cf14f9c..7aeee10f4 100644
--- a/docs/source/code_examples/fifo/fifo.out
+++ b/docs/source/code_examples/fifo/fifo.out
@@ -357,9 +357,7 @@ Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_reader.$add$f
 Removed top 23 bits (of 32) from wire fifo.$add$fifo.v:68$27_Y.
 Removed top 24 bits (of 32) from wire fifo.$flatten\fifo_reader.$add$fifo.v:20$34_Y.
 
-yosys> select -set new_cells t:$add %co t:$add %d
-
-yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_wreduce o:rdata %ci*
+yosys> show -notitle -format dot -prefix rdata_wreduce o:rdata %ci*
 
 20. Generating Graphviz representation of design.
 Writing dot description to `rdata_wreduce.dot'.
diff --git a/docs/source/code_examples/fifo/fifo.ys b/docs/source/code_examples/fifo/fifo.ys
index b6e0e34ed..57a28e63e 100644
--- a/docs/source/code_examples/fifo/fifo.ys
+++ b/docs/source/code_examples/fifo/fifo.ys
@@ -53,8 +53,7 @@ show -color maroon3 @new_cells -notitle -format dot -prefix rdata_adffe o:rdata
 # ========================================================
 
 wreduce
-select -set new_cells t:$add %co t:$add %d
-show -color maroon3 @new_cells -notitle -format dot -prefix rdata_wreduce o:rdata %ci*
+show -notitle -format dot -prefix rdata_wreduce o:rdata %ci*
 
 # unclear if this is necessary or only because of bug(s)
 opt_clean
diff --git a/docs/source/conf.py b/docs/source/conf.py
index 003887498..29d36d9c4 100644
--- a/docs/source/conf.py
+++ b/docs/source/conf.py
@@ -61,7 +61,7 @@ latex_elements = {
 
 # include todos during rewrite
 extensions.append('sphinx.ext.todo')
-todo_include_todos = True
+todo_include_todos = False
 
 # custom cmd-ref parsing/linking
 sys.path += [os.path.dirname(__file__) + "/../"]
diff --git a/docs/source/getting_started/example_synth.rst b/docs/source/getting_started/example_synth.rst
index bcbe6efc9..799b4ec48 100644
--- a/docs/source/getting_started/example_synth.rst
+++ b/docs/source/getting_started/example_synth.rst
@@ -421,7 +421,7 @@ reductions are the ones affecting ``fifo.$flatten\fifo_reader.$add$fifo.v``.
 That is the ``$add`` cell incrementing the fifo_reader address.  We can look at
 the schematic and see the output of that cell has now changed.
 
-.. TODO:: pending bugfix in :cmd:ref:`wreduce` and/or :cmd:ref:`opt_clean`
+.. todo:: pending bugfix in :cmd:ref:`wreduce` and/or :cmd:ref:`opt_clean`
 
 .. figure:: /_images/code_examples/fifo/rdata_wreduce.*
    :class: width-helper