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Resolve @cliffordwolf review, set even if !has_init
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@ -342,8 +342,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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if (!sig_e.is_fully_const())
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if (!sig_e.is_fully_const())
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return false;
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return false;
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if (sig_e != val_ep) {
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if (sig_e != val_ep) {
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if (has_init)
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mod->connect(sig_q, val_init);
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mod->connect(sig_q, val_init);
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goto delete_dff;
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goto delete_dff;
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}
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}
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}
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}
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