Merge remote-tracking branch 'upstream/master'

frontends/ilang/ilang_frontend.cc

@@ -52,11 +52,15 @@ struct IlangFrontend : public Frontend {
 		log("    -overwrite\n");
 		log("        overwrite existing modules with the same name\n");
 		log("\n");
+		log("    -lib\n");
+		log("        only create empty blackbox modules\n");
+		log("\n");
 	}
 	void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		ILANG_FRONTEND::flag_nooverwrite = false;
 		ILANG_FRONTEND::flag_overwrite = false;
+		ILANG_FRONTEND::flag_lib = false;
 
 		log_header(design, "Executing ILANG frontend.\n");
 
@@ -73,6 +77,10 @@ struct IlangFrontend : public Frontend {
 				ILANG_FRONTEND::flag_overwrite = true;
 				continue;
 			}
+			if (arg == "-lib") {
+				ILANG_FRONTEND::flag_lib = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(f, filename, args, argidx);

frontends/ilang/ilang_frontend.h

@@ -34,6 +34,7 @@ namespace ILANG_FRONTEND {
 	extern RTLIL::Design *current_design;
 	extern bool flag_nooverwrite;
 	extern bool flag_overwrite;
+	extern bool flag_lib;
 }
 
 YOSYS_NAMESPACE_END

frontends/ilang/ilang_parser.y

@@ -37,7 +37,7 @@ namespace ILANG_FRONTEND {
 	std::vector<std::vector<RTLIL::SwitchRule*>*> switch_stack;
 	std::vector<RTLIL::CaseRule*> case_stack;
 	dict<RTLIL::IdString, RTLIL::Const> attrbuf;
-	bool flag_nooverwrite, flag_overwrite;
+	bool flag_nooverwrite, flag_overwrite, flag_lib;
 	bool delete_current_module;
 }
 using namespace ILANG_FRONTEND;
@@ -98,7 +98,7 @@ module:
 		delete_current_module = false;
 		if (current_design->has($2)) {
 			RTLIL::Module *existing_mod = current_design->module($2);
-			if (!flag_overwrite && attrbuf.count("\\blackbox") && attrbuf.at("\\blackbox").as_bool()) {
+			if (!flag_overwrite && (flag_lib || (attrbuf.count("\\blackbox") && attrbuf.at("\\blackbox").as_bool()))) {
 				log("Ignoring blackbox re-definition of module %s.\n", $2);
 				delete_current_module = true;
 			} else if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
@@ -124,6 +124,8 @@ module:
 		current_module->fixup_ports();
 		if (delete_current_module)
 			delete current_module;
+		else if (flag_lib)
+			current_module->makeblackbox();
 		current_module = nullptr;
 	} EOL;
 

kernel/rtlil.cc

@@ -641,6 +641,30 @@ RTLIL::Module::~Module()
 		delete it->second;
 }
 
+void RTLIL::Module::makeblackbox()
+{
+	pool<RTLIL::Wire*> delwires;
+
+	for (auto it = wires_.begin(); it != wires_.end(); ++it)
+		if (!it->second->port_input && !it->second->port_output)
+			delwires.insert(it->second);
+
+	for (auto it = memories.begin(); it != memories.end(); ++it)
+		delete it->second;
+	memories.clear();
+
+	for (auto it = cells_.begin(); it != cells_.end(); ++it)
+		delete it->second;
+	cells_.clear();
+
+	for (auto it = processes.begin(); it != processes.end(); ++it)
+		delete it->second;
+	processes.clear();
+
+	remove(delwires);
+	set_bool_attribute("\\blackbox");
+}
+
 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
 {
 	log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));

kernel/rtlil.h

@@ -976,6 +976,7 @@ public:
 	virtual void sort();
 	virtual void check();
 	virtual void optimize();
+	virtual void makeblackbox();
 
 	void connect(const RTLIL::SigSig &conn);
 	void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);

passes/memory/memory_bram.cc

@@ -744,6 +744,7 @@ grow_read_ports:;
 			if (clken) {
 				clock_domains[pi.clocks] = clkdom;
 				clock_polarities[pi.clkpol] = clkdom.second;
+				if (!pi.make_transp)
 					read_transp[pi.transp] = transp;
 				pi.sig_clock = clkdom.first;
 				pi.sig_en = rd_en[cell_port_i];

passes/pmgen/README.md

@@ -83,8 +83,8 @@ They are declared like state variables, just using the `udata` statement:
     udata <int> min_data_width max_data_width
     udata <IdString> data_port_name
 
-They are atomatically initialzed to the default constructed value of their type
+They are automatically initialized to the default constructed value of their type
-when ther pattern matcher object is constructed.
+when the pattern matcher object is constructed.
 
 Embedded C++ code
 -----------------
@@ -158,7 +158,7 @@ Finally, `filter <expression>` narrows down the remaining list of cells. For
 performance reasons `filter` statements should only be used for things that
 can't be done using `select` and `index`.
 
-The `optional` statement marks optional matches. I.e. the matcher will also
+The `optional` statement marks optional matches. That is, the matcher will also
 explore the case where `mul` is set to `nullptr`. Without the `optional`
 statement a match may only be assigned nullptr when one of the `if` expressions
 evaluates to `false`.

passes/sat/mutate.cc

@@ -934,6 +934,32 @@ struct MutatePass : public Pass {
 			return;
 		}
 
+		if (opts.module.empty())
+			log_cmd_error("Missing -module argument.\n");
+
+		Module *module = design->module(opts.module);
+		if (module == nullptr)
+			log_cmd_error("Module %s not found.\n", log_id(opts.module));
+
+		if (opts.cell.empty())
+			log_cmd_error("Missing -cell argument.\n");
+
+		Cell *cell = module->cell(opts.cell);
+		if (cell == nullptr)
+			log_cmd_error("Cell %s not found in module %s.\n", log_id(opts.cell), log_id(opts.module));
+
+		if (opts.port.empty())
+			log_cmd_error("Missing -port argument.\n");
+
+		if (!cell->hasPort(opts.port))
+			log_cmd_error("Port %s not found on cell %s.%s.\n", log_id(opts.port), log_id(opts.module), log_id(opts.cell));
+
+		if (opts.portbit < 0)
+			log_cmd_error("Missing -portbit argument.\n");
+
+		if (GetSize(cell->getPort(opts.port)) <= opts.portbit)
+			log_cmd_error("Out-of-range -portbit argument for port %s on cell %s.%s.\n", log_id(opts.port), log_id(opts.module), log_id(opts.cell));
+
 		if (opts.mode == "inv") {
 			mutate_inv(design, opts);
 			return;
@@ -944,6 +970,12 @@ struct MutatePass : public Pass {
 			return;
 		}
 
+		if (opts.ctrlbit < 0)
+			log_cmd_error("Missing -ctrlbit argument.\n");
+
+		if (GetSize(cell->getPort(opts.port)) <= opts.ctrlbit)
+			log_cmd_error("Out-of-range -ctrlbit argument for port %s on cell %s.%s.\n", log_id(opts.port), log_id(opts.module), log_id(opts.cell));
+
 		if (opts.mode == "cnot0" || opts.mode == "cnot1") {
 			mutate_cnot(design, opts, opts.mode == "cnot1");
 			return;