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Merge remote-tracking branch 'origin/master' into xc7mux

This commit is contained in:
Eddie Hung 2019-06-10 11:02:54 -07:00
parent d5f0b73fd9 a91ea6612a
commit 352c532bb2
2 changed files with 30 additions and 1 deletions
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24
techlibs/ice40/cells_sim.v
View File

@ -1000,6 +1000,30 @@ parameter RGB1_CURRENT = "0b000000";
parameter RGB2_CURRENT = "0b000000"; parameter RGB2_CURRENT = "0b000000";
endmodule endmodule
(* blackbox *)
module SB_LED_DRV_CUR(
input EN,
output LEDPU
);
endmodule
(* blackbox *)
module SB_RGB_DRV(
input RGBLEDEN,
input RGB0PWM,
input RGB1PWM,
input RGB2PWM,
input RGBPU,
output RGB0,
output RGB1,
output RGB2
);
parameter CURRENT_MODE = "0b0";
parameter RGB0_CURRENT = "0b000000";
parameter RGB1_CURRENT = "0b000000";
parameter RGB2_CURRENT = "0b000000";
endmodule
(* blackbox *) (* blackbox *)
module SB_I2C( module SB_I2C(
input SBCLKI, input SBCLKI,

7
tests/aiger/run-test.sh
View File

@ -2,9 +2,14 @@
set -e set -e
# NB: *.aag and *.aig must contain a symbol table naming the primary
# inputs and outputs, otherwise ABC and Yosys will name them
# arbitrarily (and inconsistently with each other).
for aag in *.aag; do for aag in *.aag; do
# Since ABC cannot read *.aag, read the *.aig instead # Since ABC cannot read *.aag, read the *.aig instead
# (which would have been created by the reference aig2aig utility) # (which would have been created by the reference aig2aig utility,
# available from http://fmv.jku.at/aiger/)
../../yosys-abc -c "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v" ../../yosys-abc -c "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
../../yosys -p " ../../yosys -p "
read_verilog ${aag%.*}_ref.v read_verilog ${aag%.*}_ref.v