From 3501f8e3643bfb6cd13f8d6e1acb03fa6672fd27 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Sep 2015 11:37:15 +0200 Subject: [PATCH] Fixed memory_bram for ROMs in BRAMs with write-enable inputs --- passes/memory/memory_bram.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 824d6a6e8..f638b5bb7 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -433,7 +433,7 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram, SigSpec rd_data = cell->getPort("\\RD_DATA"); SigSpec rd_addr = cell->getPort("\\RD_ADDR"); - if (match.shuffle_enable && bram.dbits >= portinfos.at(match.shuffle_enable - 'A').enable*2 && portinfos.at(match.shuffle_enable - 'A').enable > 0) + if (match.shuffle_enable && bram.dbits >= portinfos.at(match.shuffle_enable - 'A').enable*2 && portinfos.at(match.shuffle_enable - 'A').enable > 0 && wr_ports > 0) { int bucket_size = bram.dbits / portinfos.at(match.shuffle_enable - 'A').enable; log(" Shuffle bit order to accommodate enable buckets of size %d..\n", bucket_size);