mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #4333 from YosysHQ/fix_hierarchy_generate
fix hierarchy -generate mode handling of cells
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commit
34d9a7451e
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@ -47,7 +47,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
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{
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{
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if (design->module(cell->type) != nullptr)
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if (design->module(cell->type) != nullptr)
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continue;
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continue;
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if (cell->type.begins_with("$__"))
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if (cell->type.begins_with("$") && !cell->type.begins_with("$__"))
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continue;
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continue;
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for (auto &pattern : celltypes)
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for (auto &pattern : celltypes)
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if (patmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str()))
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if (patmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str()))
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@ -0,0 +1,20 @@
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read_verilog -icells <<EOF
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module top(input [2:0] a, input [2:0] b, output [2:0] y);
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sub sub_i (.a(a[0]), .b(b[0]), .y(y[0]));
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unknown_sub sub_ii (.a(a[1]), .b(b[1]), .y(y[1]));
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$__dunder_sub sub_iii (.a(a[2]), .b(b[2]), .y(y[2]));
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endmodule
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module sub(input a, input b, output y);
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assign y = a ^ b;
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endmodule
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EOF
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hierarchy -generate unknown_sub i:a i:b o:y
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hierarchy -generate $__dunder_sub i:a i:b o:y
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hierarchy -generate $xor i:A i:B o:Y # this one is ignored
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hierarchy -top top -check
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check -assert
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