riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

read_verilog -defer should still populate module attributes

This commit is contained in:
Eddie Hung 2019-08-28 19:59:09 -07:00
parent 1fdb3fc98c
commit 34ae29295d
1 changed files with 6 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
frontends/ast/ast.cc
View File

@ -1073,11 +1073,6 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
ignoreThisSignalsInInitial = RTLIL::SigSpec(); ignoreThisSignalsInInitial = RTLIL::SigSpec();
for (auto &attr : ast->attributes) {
if (attr.second->type != AST_CONSTANT)
log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
current_module->attributes[attr.first] = attr.second->asAttrConst();
}
for (size_t i = 0; i < ast->children.size(); i++) { for (size_t i = 0; i < ast->children.size(); i++) {
AstNode *node = ast->children[i]; AstNode *node = ast->children[i];
if (node->type == AST_WIRE || node->type == AST_MEMORY) if (node->type == AST_WIRE || node->type == AST_MEMORY)
@ -1100,6 +1095,12 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
ignoreThisSignalsInInitial = RTLIL::SigSpec(); ignoreThisSignalsInInitial = RTLIL::SigSpec();
} }
for (auto &attr : ast->attributes) {
if (attr.second->type != AST_CONSTANT)
log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
current_module->attributes[attr.first] = attr.second->asAttrConst();
}
if (ast->type == AST_INTERFACE) if (ast->type == AST_INTERFACE)
current_module->set_bool_attribute("\\is_interface"); current_module->set_bool_attribute("\\is_interface");
current_module->ast = ast_before_simplify; current_module->ast = ast_before_simplify;