mirror of https://github.com/YosysHQ/yosys.git
Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit
This commit is contained in:
parent
a4238637ac
commit
34aa3532fb
|
@ -77,10 +77,8 @@ module _80_mul (A, B, Y);
|
|||
else if (Y_WIDTH < `DSP_Y_MINWIDTH)
|
||||
wire _TECHMAP_FAIL_ = 1;
|
||||
`endif
|
||||
else if (_TECHMAP_CELLTYPE_ == "$mul" && A_SIGNED != B_SIGNED)
|
||||
wire _TECHMAP_FAIL_ = 1;
|
||||
`ifdef DSP_SIGNEDONLY
|
||||
else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED)
|
||||
else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED && !B_SIGNED)
|
||||
\$mul #(
|
||||
.A_SIGNED(1),
|
||||
.B_SIGNED(1),
|
||||
|
|
Loading…
Reference in New Issue