mirror of https://github.com/YosysHQ/yosys.git
intel_alm: Fix illegal carry chains
Signed-off-by: gatecat <gatecat@ds0.me>
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eb106732d9
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@ -230,8 +230,10 @@ assign Q = ~A;
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endmodule
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endmodule
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(* abc9_box, lib_whitebox *)
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// Despite the abc9_carry attributes, this doesn't seem to stop ABC9 adding illegal fanout to the carry chain that nextpnr cannot handle.
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module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, (* abc9_carry *) input CI, output SO, (* abc9_carry *) output CO);
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// So we treat it as a total blackbox from ABC9's perspective for now.
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// (* abc9_box, lib_whitebox *)
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module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, /* (* abc9_carry *) */ input CI, output SO, /* (* abc9_carry *) */ output CO);
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parameter LUT0 = 16'h0000;
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parameter LUT0 = 16'h0000;
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parameter LUT1 = 16'h0000;
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parameter LUT1 = 16'h0000;
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@ -34,7 +34,7 @@ wire [Y_WIDTH:0] ALM_CARRY;
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// Start of carry chain
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// Start of carry chain
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generate
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generate
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if (_TECHMAP_CONSTMSK_CI_ == 1) begin
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if (_TECHMAP_CONSTMSK_CI_ == 1 && _TECHMAP_CONSTVAL_CI_ == 1'b0) begin
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assign ALM_CARRY[0] = _TECHMAP_CONSTVAL_CI_;
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assign ALM_CARRY[0] = _TECHMAP_CONSTVAL_CI_;
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end else begin
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end else begin
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MISTRAL_ALUT_ARITH #(
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MISTRAL_ALUT_ARITH #(
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@ -4,7 +4,7 @@ equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cycl
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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cd top # Constrain all select calls below inside the top module
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stat
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stat
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select -assert-count 8 t:MISTRAL_ALUT_ARITH
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select -assert-count 9 t:MISTRAL_ALUT_ARITH
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select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
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select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
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design -reset
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design -reset
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@ -14,5 +14,5 @@ equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cycl
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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cd top # Constrain all select calls below inside the top module
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stat
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stat
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select -assert-count 8 t:MISTRAL_ALUT_ARITH
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select -assert-count 9 t:MISTRAL_ALUT_ARITH
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select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
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select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
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@ -6,7 +6,7 @@ equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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cd top # Constrain all select calls below inside the top module
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select -assert-count 2 t:MISTRAL_NOT
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select -assert-count 1 t:MISTRAL_NOT
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select -assert-count 8 t:MISTRAL_ALUT_ARITH
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select -assert-count 8 t:MISTRAL_ALUT_ARITH
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select -assert-count 8 t:MISTRAL_FF
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select -assert-count 8 t:MISTRAL_FF
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select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
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select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
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@ -21,7 +21,7 @@ equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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cd top # Constrain all select calls below inside the top module
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select -assert-count 2 t:MISTRAL_NOT
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select -assert-count 1 t:MISTRAL_NOT
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select -assert-count 8 t:MISTRAL_ALUT_ARITH
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select -assert-count 8 t:MISTRAL_ALUT_ARITH
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select -assert-count 8 t:MISTRAL_FF
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select -assert-count 8 t:MISTRAL_FF
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select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
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select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
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