From 28cfc75a902574c3ad96876d2f5e01af6c583bac Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Wed, 15 Aug 2018 19:56:30 +0300
Subject: [PATCH 01/35] A few minor enhancements to specify block parsing. Just
 remember specify blocks are parsed but ignored.

---
 frontends/verilog/verilog_parser.y | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 78cac5543..61da12b76 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -688,8 +688,8 @@ path_declaration :
 	;
 
 simple_path_declaration :
-	parallel_path_description '=' path_delay_value ';'
-	// | full_path_description '=' path_delay_value ';'
+	parallel_path_description '=' path_delay_value ';' |
+	full_path_description '=' path_delay_value ';'
 	;
 
 path_delay_value :
@@ -723,6 +723,17 @@ list_of_path_delay_expressions :
 parallel_path_description :
 	'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ;
 
+full_path_description :
+	'(' list_of_path_inputs opt_polarity_operator '*' '>' list_of_path_outputs ')' ;
+
+list_of_path_inputs :
+	specify_input_terminal_descriptor |
+	list_of_path_inputs ',' specify_input_terminal_descriptor ;
+	
+list_of_path_outputs :
+	specify_output_terminal_descriptor |
+	list_of_path_outputs ',' specify_output_terminal_descriptor ;
+	
 opt_polarity_operator :
 	'+'
 	| '-'

From 9f91c62348c533d0d0d167a393bab284b2c6de8d Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Wed, 15 Aug 2018 17:15:44 -0400
Subject: [PATCH 02/35] Fix run_command() when using -format and -viewer in
 show pass.

---
 passes/cmds/show.cc | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index ec04418fa..fa88cd668 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -817,14 +817,30 @@ struct ShowPass : public Pass {
 			log_cmd_error("Nothing there to show.\n");
 
 		if (format != "dot" && !format.empty()) {
-			std::string cmd = stringf("dot -T%s '%s' > '%s.new' && mv '%s.new' '%s'", format.c_str(), dot_file.c_str(), out_file.c_str(), out_file.c_str(), out_file.c_str());
+			#ifdef _WIN32
+				// system()/cmd.exe does not understand single quotes on Windows.
+				#define DOT_CMD "dot -T%s \"%s\" > \"%s.new\" && move \"%s.new\" \"%s\""
+			#else
+				#define DOT_CMD "dot -T%s '%s' > '%s.new' && mv '%s.new' '%s'"
+			#endif
+			std::string cmd = stringf(DOT_CMD, format.c_str(), dot_file.c_str(), out_file.c_str(), out_file.c_str(), out_file.c_str());
+			#undef DOT_CMD
 			log("Exec: %s\n", cmd.c_str());
 			if (run_command(cmd) != 0)
 				log_cmd_error("Shell command failed!\n");
 		}
 
 		if (!viewer_exe.empty()) {
-			std::string cmd = stringf("%s '%s' &", viewer_exe.c_str(), out_file.c_str());
+			#ifdef _WIN32
+				// system()/cmd.exe does not understand single quotes nor
+				// background tasks on Windows. So we have to pause yosys
+				// until the viewer exits.
+				#define VIEW_CMD "%s \"%s\""
+			#else
+				#define VIEW_CMD "%s '%s' &"
+			#endif
+			std::string cmd = stringf(VIEW_CMD, viewer_exe.c_str(), out_file.c_str());
+			#undef VIEW_CMD
 			log("Exec: %s\n", cmd.c_str());
 			if (run_command(cmd) != 0)
 				log_cmd_error("Shell command failed!\n");

From 7ce7ea2eb4903058ac4560d7b192cb5ed02aed89 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Wed, 15 Aug 2018 17:16:07 -0400
Subject: [PATCH 03/35] Update show pass documentation with Windows caveats.

---
 passes/cmds/show.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index fa88cd668..a48873244 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -584,6 +584,7 @@ struct ShowPass : public Pass {
 		log("\n");
 		log("    -viewer <viewer>\n");
 		log("        Run the specified command with the graphics file as parameter.\n");
+		log("        On Windows, this pauses yosys until the viewer exits.\n");
 		log("\n");
 		log("    -format <format>\n");
 		log("        Generate a graphics file in the specified format. Use 'dot' to just\n");
@@ -645,7 +646,7 @@ struct ShowPass : public Pass {
 		log("        do not add the module name as graph title to the dot file\n");
 		log("\n");
 		log("When no <format> is specified, 'dot' is used. When no <format> and <viewer> is\n");
-		log("specified, 'xdot' is used to display the schematic.\n");
+		log("specified, 'xdot' is used to display the schematic (POSIX systems only).\n");
 		log("\n");
 		log("The generated output files are '~/.yosys_show.dot' and '~/.yosys_show.<format>',\n");
 		log("unless another prefix is specified using -prefix <prefix>.\n");

From 3e20788c24d2b0472fa9e3ecee31b636c5866d8d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 18 Aug 2018 14:00:55 +0200
Subject: [PATCH 04/35] Added gcc-static for easier cross compilation

---
 Makefile | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index eed4e8f23..c2a3293ae 100644
--- a/Makefile
+++ b/Makefile
@@ -156,6 +156,14 @@ LD = gcc
 CXXFLAGS += -std=c++11 -Os
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
 
+else ifeq ($(CONFIG),gcc-static)
+LD = $(CXX)
+LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
+LDLIBS := -static $(filter-out -lrt,$(LDLIBS))
+CXXFLAGS += -std=c++11 -Os
+ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" LIBS="-static -lm -ldl -pthread" OPTFLAGS="-O" \
+                       ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable" ABC_USE_NO_READLINE=1
+
 else ifeq ($(CONFIG),gcc-4.8)
 CXX = gcc-4.8
 LD = gcc-4.8
@@ -671,6 +679,12 @@ config-clang: clean
 config-gcc: clean
 	echo 'CONFIG := gcc' > Makefile.conf
 
+config-gcc-static: clean
+	echo 'CONFIG := gcc-static' > Makefile.conf
+	echo 'ENABLE_PLUGINS := 0' >> Makefile.conf
+	echo 'ENABLE_READLINE := 0' >> Makefile.conf
+	echo 'ENABLE_TCL := 0' >> Makefile.conf
+
 config-gcc-4.8: clean
 	echo 'CONFIG := gcc-4.8' > Makefile.conf
 
@@ -712,5 +726,5 @@ echo-git-rev:
 -include techlibs/*/*.d
 
 .PHONY: all top-all abc test install install-abc manual clean mrproper qtcreator
-.PHONY: config-clean config-clang config-gcc config-gcc-4.8 config-gprof config-sudo
+.PHONY: config-clean config-clang config-gcc config-gcc-static config-gcc-4.8 config-gprof config-sudo
 

From 539053ab68d7a124f0c710e3fbd87aba8ee8b0aa Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 18 Aug 2018 14:14:17 +0200
Subject: [PATCH 05/35] Added option to disable -fPIC on unsupported platforms

---
 Makefile | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Makefile b/Makefile
index c2a3293ae..c2a076229 100644
--- a/Makefile
+++ b/Makefile
@@ -160,6 +160,9 @@ else ifeq ($(CONFIG),gcc-static)
 LD = $(CXX)
 LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
 LDLIBS := -static $(filter-out -lrt,$(LDLIBS))
+ifeq ($(NO_FPIC),1)
+CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
+endif
 CXXFLAGS += -std=c++11 -Os
 ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" LIBS="-static -lm -ldl -pthread" OPTFLAGS="-O" \
                        ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable" ABC_USE_NO_READLINE=1

From 45740236b6b0aa8d445fb3fea8d8c1ec497be3cf Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 18 Aug 2018 15:11:58 +0200
Subject: [PATCH 06/35] Enable propagating ARCHFLAGS

---
 Makefile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index c2a076229..024b216f0 100644
--- a/Makefile
+++ b/Makefile
@@ -164,8 +164,8 @@ ifeq ($(NO_FPIC),1)
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
 endif
 CXXFLAGS += -std=c++11 -Os
-ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" LIBS="-static -lm -ldl -pthread" OPTFLAGS="-O" \
-                       ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable" ABC_USE_NO_READLINE=1
+ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" ABC_USE_LIBSTDCXX=1 LIBS="-static -lm -lpthread" OPTFLAGS="-O" \
+                       ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable $(ARCHFLAGS)" ABC_USE_NO_READLINE=1
 
 else ifeq ($(CONFIG),gcc-4.8)
 CXX = gcc-4.8

From 443865ab870248aed91700686160d36ed616503d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 18 Aug 2018 18:21:28 +0200
Subject: [PATCH 07/35] respect DISABLE_ABC_THREADS if used

---
 Makefile | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index 024b216f0..c3e3a4b47 100644
--- a/Makefile
+++ b/Makefile
@@ -159,13 +159,16 @@ ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
 else ifeq ($(CONFIG),gcc-static)
 LD = $(CXX)
 LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
-LDLIBS := -static $(filter-out -lrt,$(LDLIBS))
+LDLIBS := -static $(filter-out -lrt,$(LDLIBS)) 
 ifeq ($(NO_FPIC),1)
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
 endif
 CXXFLAGS += -std=c++11 -Os
-ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" ABC_USE_LIBSTDCXX=1 LIBS="-static -lm -lpthread" OPTFLAGS="-O" \
+ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" ABC_USE_LIBSTDCXX=1 LIBS="-lm -lpthread -static" OPTFLAGS="-O" \
                        ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable $(ARCHFLAGS)" ABC_USE_NO_READLINE=1
+ifeq ($(DISABLE_ABC_THREADS),1)
+ABCMKARGS += "ABC_USE_NO_PTHREADS=1"
+endif
 
 else ifeq ($(CONFIG),gcc-4.8)
 CXX = gcc-4.8

From 75d185294362ae9ed2fbb08e5348cbdf113c3e8f Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 18 Aug 2018 19:17:02 +0200
Subject: [PATCH 08/35] no -fPIC for any static build

---
 Makefile | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/Makefile b/Makefile
index c3e3a4b47..c1e5c789d 100644
--- a/Makefile
+++ b/Makefile
@@ -159,10 +159,8 @@ ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
 else ifeq ($(CONFIG),gcc-static)
 LD = $(CXX)
 LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
-LDLIBS := -static $(filter-out -lrt,$(LDLIBS)) 
-ifeq ($(NO_FPIC),1)
+LDLIBS := $(filter-out -lrt,$(LDLIBS)) 
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
-endif
 CXXFLAGS += -std=c++11 -Os
 ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" ABC_USE_LIBSTDCXX=1 LIBS="-lm -lpthread -static" OPTFLAGS="-O" \
                        ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable $(ARCHFLAGS)" ABC_USE_NO_READLINE=1

From 95241c8f4d32c5bd644bef71509965a82582264c Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Mon, 20 Aug 2018 00:08:08 +0300
Subject: [PATCH 09/35] Yosys can now parse
 https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v
 , (specify block ignored). Must use 'read_verilog -defer' due to a parameter
 not assigned a default value.

---
 frontends/verilog/verilog_parser.y | 32 ++++++++++++++++++++----------
 1 file changed, 22 insertions(+), 10 deletions(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 61da12b76..58a6824d1 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -654,7 +654,7 @@ specify_item:
 	// | pulsestyle_declaration
 	// | showcancelled_declaration
 	| path_declaration
-	// | system_timing_declaration
+	| system_timing_declaration
 	;
 
 specparam_declaration:
@@ -693,8 +693,8 @@ simple_path_declaration :
 	;
 
 path_delay_value :
-	//list_of_path_delay_expressions
-	'(' list_of_path_delay_expressions ')'
+	list_of_path_delay_expressions |
+	%prec '(' list_of_path_delay_expressions ')'
 	;
 
 list_of_path_delay_expressions :
@@ -724,12 +724,17 @@ parallel_path_description :
 	'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ;
 
 full_path_description :
-	'(' list_of_path_inputs opt_polarity_operator '*' '>' list_of_path_outputs ')' ;
+	'(' list_of_path_inputs '*' '>' list_of_path_outputs ')' ;
 
+// This was broken into 2 rules to solve shift/reduce conflicts
 list_of_path_inputs :
-	specify_input_terminal_descriptor |
-	list_of_path_inputs ',' specify_input_terminal_descriptor ;
-	
+	specify_input_terminal_descriptor                  opt_polarity_operator  |
+	specify_input_terminal_descriptor more_path_inputs opt_polarity_operator ;
+
+more_path_inputs :
+    ',' specify_input_terminal_descriptor |
+    more_path_inputs ',' specify_input_terminal_descriptor ;
+
 list_of_path_outputs :
 	specify_output_terminal_descriptor |
 	list_of_path_outputs ',' specify_output_terminal_descriptor ;
@@ -747,11 +752,18 @@ specify_input_terminal_descriptor :
 specify_output_terminal_descriptor :
 	TOK_ID ;
 
-/*
 system_timing_declaration :
-	;
-*/
+	TOK_ID '(' system_timing_args ')' ';' ;
 
+system_timing_arg :
+	TOK_POSEDGE TOK_ID |
+	TOK_NEGEDGE TOK_ID |
+	expr ;
+
+system_timing_args :
+	system_timing_arg |
+	system_timing_args ',' system_timing_arg ;
+ 
 /*
 t_path_delay_expression :
 	path_delay_expression;

From fbfc677df3e54798faba3ab2f27c270759b96507 Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Mon, 20 Aug 2018 17:27:45 +0300
Subject: [PATCH 10/35] Fixed all known specify/endspecify issues, without
 breaking 'make test'. Some the of parser fixes may look strange but they were
 needed to avoid shift/reduce conflicts, due to the explicit parentheses in
 path_delay_value, and the mintypmax values without parentheses

---
 frontends/verilog/verilog_parser.y | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 58a6824d1..2389d7d31 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -682,22 +682,23 @@ showcancelled_declaration :
 */
 
 path_declaration :
-	simple_path_declaration
+	simple_path_declaration ';'
 	// | edge_sensitive_path_declaration
 	// | state_dependent_path_declaration
 	;
 
 simple_path_declaration :
-	parallel_path_description '=' path_delay_value ';' |
-	full_path_description '=' path_delay_value ';'
+	parallel_path_description '=' path_delay_value |
+	full_path_description '=' path_delay_value
 	;
 
 path_delay_value :
-	list_of_path_delay_expressions |
-	%prec '(' list_of_path_delay_expressions ')'
+	'(' path_delay_expression list_of_path_delay_extra_expressions ')'
+	|     path_delay_expression
+	|     path_delay_expression list_of_path_delay_extra_expressions
 	;
 
-list_of_path_delay_expressions :
+list_of_path_delay_extra_expressions :
 /*
 	t_path_delay_expression
 	| trise_path_delay_expression ',' tfall_path_delay_expression
@@ -709,12 +710,11 @@ list_of_path_delay_expressions :
 	  t0x_path_delay_expression ',' tx1_path_delay_expression ',' t1x_path_delay_expression ','
 	  tx0_path_delay_expression ',' txz_path_delay_expression ',' tzx_path_delay_expression
 */
-	path_delay_expression
-	| path_delay_expression ',' path_delay_expression
-	| path_delay_expression ',' path_delay_expression ',' path_delay_expression
-	| path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
+	',' path_delay_expression
+	|  ',' path_delay_expression ',' path_delay_expression
+	|  ',' path_delay_expression ',' path_delay_expression ','
 	  path_delay_expression ',' path_delay_expression ',' path_delay_expression
-	| path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
+	|  ',' path_delay_expression ',' path_delay_expression ','
 	  path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
 	  path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
 	  path_delay_expression ',' path_delay_expression ',' path_delay_expression
@@ -815,7 +815,7 @@ tzx_path_delay_expression :
 */
 
 path_delay_expression :
-	constant_mintypmax_expression;
+	constant_expression;
 
 constant_mintypmax_expression :
 	constant_expression

From 4b02ee91627c49bd4ea0e89d6c8531283501a24b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 22 Aug 2018 13:30:22 +0200
Subject: [PATCH 11/35] Add Verific -work parameter

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 26 ++++++++++++++++++--------
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index b8c0375ce..cb31634dd 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1837,6 +1837,7 @@ struct VerificPass : public Pass {
 		log("Built with Verific %s, released at %s.\n", release_str, release_tmstr);
 
 		int argidx = 1;
+		std::string work = "work";
 
 		if (GetSize(args) > argidx && (args[argidx] == "-set-error" || args[argidx] == "-set-warning" ||
 				args[argidx] == "-set-info" || args[argidx] == "-set-ignore"))
@@ -1895,6 +1896,15 @@ struct VerificPass : public Pass {
 			goto check_error;
 		}
 
+		for (; argidx < GetSize(args); argidx++)
+		{
+			if (args[argidx] == "-work" && argidx+1 < GetSize(args)) {
+				work = args[++argidx];
+				continue;
+			}
+			break;
+		}
+
 		if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" ||
 				args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal"))
 		{
@@ -1942,7 +1952,7 @@ struct VerificPass : public Pass {
 			while (argidx < GetSize(args))
 				file_names.Insert(args[argidx++].c_str());
 
-			if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, "work", veri_file::MFCU))
+			if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU))
 					log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
 
 			verific_import_pending = true;
@@ -1952,7 +1962,7 @@ struct VerificPass : public Pass {
 		if (GetSize(args) > argidx && args[argidx] == "-vhdl87") {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str());
 			for (argidx++; argidx < GetSize(args); argidx++)
-				if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_87))
+				if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_87))
 					log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args[argidx].c_str());
 			verific_import_pending = true;
 			goto check_error;
@@ -1961,7 +1971,7 @@ struct VerificPass : public Pass {
 		if (GetSize(args) > argidx && args[argidx] == "-vhdl93") {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
 			for (argidx++; argidx < GetSize(args); argidx++)
-				if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_93))
+				if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_93))
 					log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args[argidx].c_str());
 			verific_import_pending = true;
 			goto check_error;
@@ -1970,7 +1980,7 @@ struct VerificPass : public Pass {
 		if (GetSize(args) > argidx && args[argidx] == "-vhdl2k") {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
 			for (argidx++; argidx < GetSize(args); argidx++)
-				if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2K))
+				if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_2K))
 					log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args[argidx].c_str());
 			verific_import_pending = true;
 			goto check_error;
@@ -1979,7 +1989,7 @@ struct VerificPass : public Pass {
 		if (GetSize(args) > argidx && (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl")) {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
 			for (argidx++; argidx < GetSize(args); argidx++)
-				if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2008))
+				if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_2008))
 					log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args[argidx].c_str());
 			verific_import_pending = true;
 			goto check_error;
@@ -2089,8 +2099,8 @@ struct VerificPass : public Pass {
 #else
 				log("Running hier_tree::ElaborateAll().\n");
 
-				VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1);
-				VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1);
+				VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
+				VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1);
 
 				Array veri_libs, vhdl_libs;
 				if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
@@ -2137,7 +2147,7 @@ struct VerificPass : public Pass {
 						continue;
 					}
 
-					VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1);
+					VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
 					VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(name);
 					if (vhdl_unit) {
 						log("Adding VHDL unit '%s' to elaboration queue.\n", name);

From 408077769ff022f78f10ec1ffb60926361f8dc9f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 22 Aug 2018 17:22:24 +0200
Subject: [PATCH 12/35] Add "verific -work" help message

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index cb31634dd..1dd6d7e24 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1706,11 +1706,18 @@ struct VerificPass : public Pass {
 		log("\n");
 		log("Like -sv, but define FORMAL instead of SYNTHESIS.\n");
 		log("\n");
+		log("\n");
 		log("    verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
 		log("\n");
 		log("Load the specified VHDL files into Verific.\n");
 		log("\n");
 		log("\n");
+		log("    verific -work <libname> {-sv|-vhdl|...} <hdl-file>\n");
+		log("\n");
+		log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");
+		log("(default library when -work is not present: \"work\")\n");
+		log("\n");
+		log("\n");
 		log("    verific -vlog-incdir <directory>..\n");
 		log("\n");
 		log("Add Verilog include directories.\n");

From 042b3074f8096212b3f2114d353b2ec75818810b Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Thu, 23 Aug 2018 15:19:46 +0300
Subject: [PATCH 13/35] Added -no_dump_ptr flag for AST dump options in
 'read_verilog' This option disables the memory pointer display. This is
 useful when diff'ing different dumps because otherwise the node pointers
 makes every diff line different when the AST content is the same.

---
 frontends/ast/ast.cc                  | 15 +++++++++------
 frontends/ast/ast.h                   |  4 ++--
 frontends/verilog/verilog_frontend.cc | 10 +++++++++-
 3 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 7c72a50d9..e79be953a 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -44,7 +44,7 @@ namespace AST {
 
 // instanciate global variables (private API)
 namespace AST_INTERNAL {
-	bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
+	bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
 	bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
 	AstNode *current_ast, *current_ast_mod;
 	std::map<std::string, AstNode*> current_scope;
@@ -267,10 +267,12 @@ void AstNode::dumpAst(FILE *f, std::string indent) const
 	std::string type_name = type2str(type);
 	fprintf(f, "%s%s <%s:%d>", indent.c_str(), type_name.c_str(), filename.c_str(), linenum);
 
-	if (id2ast)
-		fprintf(f, " [%p -> %p]", this, id2ast);
-	else
-		fprintf(f, " [%p]", this);
+	if (!flag_no_dump_ptr) {
+		if (id2ast)
+			fprintf(f, " [%p -> %p]", this, id2ast);
+		else
+			fprintf(f, " [%p]", this);
+	}
 
 	if (!str.empty())
 		fprintf(f, " str='%s'", str.c_str());
@@ -1008,12 +1010,13 @@ static AstModule* process_module(AstNode *ast, bool defer)
 }
 
 // create AstModule instances for all modules in the AST tree and add them to 'design'
-void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil,
+void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil,
 		bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire)
 {
 	current_ast = ast;
 	flag_dump_ast1 = dump_ast1;
 	flag_dump_ast2 = dump_ast2;
+	flag_no_dump_ptr = no_dump_ptr;
 	flag_dump_vlog = dump_vlog;
 	flag_dump_rtlil = dump_rtlil;
 	flag_nolatches = nolatches;
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index d94199643..7e97bdb3b 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -274,7 +274,7 @@ namespace AST
 	};
 
 	// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
-	void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit,
+	void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit,
 			bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire);
 
 	// parametric modules are supported directly by the AST library
@@ -305,7 +305,7 @@ namespace AST
 namespace AST_INTERNAL
 {
 	// internal state variables
-	extern bool flag_dump_ast1, flag_dump_ast2, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
+	extern bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
 	extern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
 	extern AST::AstNode *current_ast, *current_ast_mod;
 	extern std::map<std::string, AST::AstNode*> current_scope;
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 911e36112..8dcc7c5aa 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -78,6 +78,9 @@ struct VerilogFrontend : public Frontend {
 		log("    -dump_ast2\n");
 		log("        dump abstract syntax tree (after simplification)\n");
 		log("\n");
+		log("    -no_dump_ptr\n");
+		log("        do not include hex memory addresses in dump (easier to diff dumps)\n");
+		log("\n");
 		log("    -dump_vlog\n");
 		log("        dump ast as Verilog code (after simplification)\n");
 		log("\n");
@@ -184,6 +187,7 @@ struct VerilogFrontend : public Frontend {
 	{
 		bool flag_dump_ast1 = false;
 		bool flag_dump_ast2 = false;
+		bool flag_no_dump_ptr = false;
 		bool flag_dump_vlog = false;
 		bool flag_dump_rtlil = false;
 		bool flag_nolatches = false;
@@ -241,6 +245,10 @@ struct VerilogFrontend : public Frontend {
 				flag_dump_ast2 = true;
 				continue;
 			}
+			if (arg == "-no_dump_ptr") {
+				flag_no_dump_ptr = true;
+				continue;
+			}
 			if (arg == "-dump_vlog") {
 				flag_dump_vlog = true;
 				continue;
@@ -381,7 +389,7 @@ struct VerilogFrontend : public Frontend {
 		if (flag_nodpi)
 			error_on_dpi_function(current_ast);
 
-		AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
+		AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
 
 		if (!flag_nopp)
 			delete lexin;

From 93d19dc2fb35335607e67cab8ecf5ebe28268a1f Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Thu, 23 Aug 2018 14:35:11 -0700
Subject: [PATCH 14/35] Add support for module instances. Don't pad logical
 operands to one bit. Use operand width and signedness in $reduce_bool. Shift
 amounts are unsigned and shouldn't be padded. Group "is invalid" with the
 wire declaration, not its use (otherwise it is incorrectly wired to 0).

---
 backends/firrtl/firrtl.cc | 139 +++++++++++++++++++++++++++++++++-----
 1 file changed, 122 insertions(+), 17 deletions(-)

diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 4f56f498c..14fae1a83 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -28,10 +28,32 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+bool defparam, noattr;
 pool<string> used_names;
 dict<IdString, string> namecache;
 int autoid_counter;
 
+typedef unsigned FDirection;
+static const FDirection NODIRECTION = 0x0;
+static const FDirection IN = 0x1;
+static const FDirection OUT = 0x2;
+static const FDirection INOUT = 0x3;
+
+// Get a port direction with respect to a specific module.
+FDirection getPortFDirection(IdString id, Module *module)
+{
+	Wire *wire = module->wires_.at(id);
+	FDirection direction = NODIRECTION;
+	if (wire && wire->port_id)
+	{
+		if (wire->port_input)
+			direction |= IN;
+		if (wire->port_output)
+			direction |= OUT;
+	}
+	return direction;
+}
+
 string next_id()
 {
 	string new_id;
@@ -77,6 +99,8 @@ struct FirrtlWorker
 
 	dict<SigBit, pair<string, int>> reverse_wire_map;
 	string unconn_id;
+	RTLIL::Design *design;
+	std::string indent;
 
 	void register_reverse_wire_map(string id, SigSpec sig)
 	{
@@ -84,11 +108,11 @@ struct FirrtlWorker
 			reverse_wire_map[sig[i]] = make_pair(id, i);
 	}
 
-	FirrtlWorker(Module *module, std::ostream &f) : module(module), f(f)
+	FirrtlWorker(Module *module, std::ostream &f, RTLIL::Design *theDesign) : module(module), f(f), design(theDesign), indent("    ")
 	{
 	}
 
-	string make_expr(SigSpec sig)
+	string make_expr(const SigSpec &sig)
 	{
 		string expr;
 
@@ -135,6 +159,74 @@ struct FirrtlWorker
 		return expr;
 	}
 
+	std::string fid(RTLIL::IdString internal_id)
+	{
+		const char *str = internal_id.c_str();
+		return *str == '\\' ? str + 1 : str;
+	}
+
+
+	std::string cellname(RTLIL::Cell *cell)
+	{
+		return fid(cell->name).c_str();
+	}
+
+	void process_instance(RTLIL::Cell *cell, vector<string> &wire_exprs)
+	{
+		// TODO: Deal with cell attributes
+		if (!noattr && !cell->attributes.empty()) {
+
+		}
+		std::string cell_type = fid(cell->type);
+
+		// TODO: Deal with cell parameters
+		if (!defparam && cell->parameters.size() > 0) {
+
+		}
+
+		std::string cell_name = cellname(cell);
+		std::string cell_name_comment;
+		if (cell_name != fid(cell->name))
+			cell_name_comment = " /* " + fid(cell->name) + " */ ";
+		else
+			cell_name_comment = "";
+		// Find the module corresponding to this instance.
+		auto instModule = design->module(cell->type);
+		wire_exprs.push_back(stringf("%s" "inst %s%s of %s", indent.c_str(), cell_name.c_str(), cell_name_comment.c_str(), cell_type.c_str()));
+
+		for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) {
+			if (it->second.size() > 0) {
+				const SigSpec &secondSig = it->second;
+				const std::string firstName = cell_name + "." + make_id(it->first);
+				const std::string secondName = make_expr(secondSig);
+				// Find the direction for this port.
+				FDirection dir = getPortFDirection(it->first, instModule);
+				std::string source, sink;
+				switch (dir) {
+					case INOUT:
+						log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", log_id(cell_type), log_signal(it->second));
+					case OUT:
+						source = firstName;
+						sink = secondName;
+						break;
+					case NODIRECTION:
+						log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", log_id(cell_type), log_signal(it->second));
+						/* FALL_THROUGH */
+					case IN:
+						source = secondName;
+						sink = firstName;
+						break;
+					default:
+						log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", log_id(cell_type), log_signal(it->second), dir);
+						break;
+				}
+				wire_exprs.push_back(stringf("\n%s%s <= %s", indent.c_str(), sink.c_str(), source.c_str()));
+			}
+		}
+		wire_exprs.push_back(stringf("\n"));
+
+	}
+
 	void run()
 	{
 		f << stringf("  module %s:\n", make_id(module->name));
@@ -142,21 +234,28 @@ struct FirrtlWorker
 
 		for (auto wire : module->wires())
 		{
+			const auto wireName = make_id(wire->name);
 			if (wire->port_id)
 			{
 				if (wire->port_input && wire->port_output)
 					log_error("Module port %s.%s is inout!\n", log_id(module), log_id(wire));
 				port_decls.push_back(stringf("    %s %s: UInt<%d>\n", wire->port_input ? "input" : "output",
-						make_id(wire->name), wire->width));
+						wireName, wire->width));
 			}
 			else
 			{
-				wire_decls.push_back(stringf("    wire %s: UInt<%d>\n", make_id(wire->name), wire->width));
+				wire_decls.push_back(stringf("    wire %s: UInt<%d>\n", wireName, wire->width));
 			}
 		}
 
 		for (auto cell : module->cells())
 		{
+		  // Is this cell is a module instance?
+			if (cell->type[0] != '$')
+			{
+				process_instance(cell, wire_exprs);
+				continue;
+			}
 			if (cell->type.in("$not", "$logic_not", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_bool", "$reduce_xnor"))
 			{
 				string y_id = make_id(cell->name);
@@ -169,7 +268,10 @@ struct FirrtlWorker
 					a_expr = "asSInt(" + a_expr + ")";
 				}
 
-				a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
+				// Don't use the results of logical operations (a single bit) to control padding
+				if (!(cell->type.in("$eq", "$eqx", "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$reduce_bool", "$logic_not") && y_width == 1) ) {
+					a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
+				}
 
 				string primop;
                                 bool always_uint = false;
@@ -187,9 +289,12 @@ struct FirrtlWorker
                                         a_expr = stringf("xorr(%s)", a_expr.c_str());
                                 }
 				if (cell->type == "$reduce_bool") {
-                                        primop = "neq";
-                                        a_expr = stringf("%s, UInt(0)", a_expr.c_str());
-                                }
+					primop = "neq";
+					// Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand.
+					bool a_signed = cell->parameters.at("\\A_SIGNED").as_bool();
+					int a_width =  cell->parameters.at("\\A_WIDTH").as_int();
+					a_expr = stringf("%s, %cInt<%d>(0)", a_expr.c_str(), a_signed ? 'S' : 'U', a_width);
+				}
 
 				string expr = stringf("%s(%s)", primop.c_str(), a_expr.c_str());
 
@@ -215,16 +320,16 @@ struct FirrtlWorker
 				if (cell->parameters.at("\\A_SIGNED").as_bool()) {
 					a_expr = "asSInt(" + a_expr + ")";
 				}
-				if (cell->parameters.at("\\A_SIGNED").as_bool()  & (cell->type != "$shr")) {
-					b_expr = "asSInt(" + b_expr + ")";
+				// Shift amount is always unsigned, and needn't be padded to result width.
+				if (!cell->type.in("$shr", "$sshr", "$shl", "$sshl")) {
+					if (cell->parameters.at("\\B_SIGNED").as_bool()) {
+						b_expr = "asSInt(" + b_expr + ")";
+					}
+					b_expr = stringf("pad(%s, %d)", b_expr.c_str(), y_width);
 				}
 
 				a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
 
-				if ((cell->type != "$shl") && (cell->type != "$sshl")) {
-				        b_expr = stringf("pad(%s, %d)", b_expr.c_str(), y_width);
-                                }
-
 				if (cell->parameters.at("\\A_SIGNED").as_bool()  & (cell->type == "$shr")) {
 					a_expr = "asUInt(" + a_expr + ")";
 				}
@@ -494,14 +599,14 @@ struct FirrtlWorker
 			if (is_valid) {
 				if (make_unconn_id) {
 					wire_decls.push_back(stringf("    wire %s: UInt<1>\n", unconn_id.c_str()));
-					cell_exprs.push_back(stringf("    %s is invalid\n", unconn_id.c_str()));
+					wire_decls.push_back(stringf("    %s is invalid\n", unconn_id.c_str()));
 				}
 				wire_exprs.push_back(stringf("    %s <= %s\n", make_id(wire->name), expr.c_str()));
 			} else {
 				if (make_unconn_id) {
 					unconn_id.clear();
 				}
-				wire_exprs.push_back(stringf("    %s is invalid\n", make_id(wire->name)));
+				wire_decls.push_back(stringf("    %s is invalid\n", make_id(wire->name)));
 			}
 		}
 
@@ -570,7 +675,7 @@ struct FirrtlBackend : public Backend {
 
 		for (auto module : design->modules())
 		{
-			FirrtlWorker worker(module, *f);
+			FirrtlWorker worker(module, *f, design);
 			worker.run();
 		}
 

From 306a010e199d9318472c9c08eb16117bd83c7257 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 25 Aug 2018 16:20:44 +0200
Subject: [PATCH 15/35] static link flag on main executable

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index c1e5c789d..18bf303b1 100644
--- a/Makefile
+++ b/Makefile
@@ -158,7 +158,7 @@ ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
 
 else ifeq ($(CONFIG),gcc-static)
 LD = $(CXX)
-LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
+LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -static
 LDLIBS := $(filter-out -lrt,$(LDLIBS)) 
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
 CXXFLAGS += -std=c++11 -Os

From 9e845bd25460d7b8287cf3ea5147040689940f49 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 27 Aug 2018 13:27:05 +0200
Subject: [PATCH 16/35] Add ENABLE_GCOV build option

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 Makefile | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/Makefile b/Makefile
index 18bf303b1..7eb3971f7 100644
--- a/Makefile
+++ b/Makefile
@@ -19,6 +19,7 @@ ENABLE_LIBYOSYS := 0
 ENABLE_PROTOBUF := 0
 
 # other configuration flags
+ENABLE_GCOV := 0
 ENABLE_GPROF := 0
 ENABLE_DEBUG := 0
 ENABLE_NDEBUG := 0
@@ -312,6 +313,11 @@ endif
 endif
 endif
 
+ifeq ($(ENABLE_GCOV),1)
+CXXFLAGS += --coverage
+LDFLAGS += --coverage
+endif
+
 ifeq ($(ENABLE_GPROF),1)
 CXXFLAGS += -pg
 LDFLAGS += -pg
@@ -709,6 +715,11 @@ config-msys2: clean
 config-msys2-64: clean
 	echo 'CONFIG := msys2-64' > Makefile.conf
 
+config-gcov: clean
+	echo 'CONFIG := gcc' > Makefile.conf
+	echo 'ENABLE_GCOV := 1' >> Makefile.conf
+	echo 'ENABLE_DEBUG := 1' >> Makefile.conf
+
 config-gprof: clean
 	echo 'CONFIG := gcc' > Makefile.conf
 	echo 'ENABLE_GPROF := 1' >> Makefile.conf

From ddc1761f1a443ea9560c67cfc126160ba7254a39 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 27 Aug 2018 14:22:21 +0200
Subject: [PATCH 17/35] Add "make coverage"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 .gitignore                        | 4 ++++
 Makefile                          | 8 +++++++-
 frontends/ilang/.gitignore        | 2 +-
 frontends/ilang/Makefile.inc      | 7 +++----
 frontends/ilang/ilang_lexer.l     | 2 +-
 frontends/verilog/.gitignore      | 2 +-
 frontends/verilog/Makefile.inc    | 7 +++----
 frontends/verilog/verilog_lexer.l | 2 +-
 8 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/.gitignore b/.gitignore
index cd624f233..4fce690ec 100644
--- a/.gitignore
+++ b/.gitignore
@@ -2,6 +2,8 @@
 *.d
 .*.swp
 *.gch
+*.gcda
+*.gcno
 /.cproject
 /.project
 /.settings
@@ -10,6 +12,8 @@
 /qtcreator.config
 /qtcreator.creator
 /qtcreator.creator.user
+/coverage.info
+/coverage_html
 /Makefile.conf
 /abc
 /viz.js
diff --git a/Makefile b/Makefile
index 7eb3971f7..39a361a5f 100644
--- a/Makefile
+++ b/Makefile
@@ -650,6 +650,12 @@ clean-abc:
 mrproper: clean
 	git clean -xdf
 
+coverage:
+	./yosys -qp 'help; help -all'
+	rm -rf coverage.info coverage_html
+	lcov --capture -d . --no-external -o coverage.info
+	genhtml coverage.info --output-directory coverage_html
+
 qtcreator:
 	{ for file in $(basename $(OBJS)); do \
 		for prefix in cc y l; do if [ -f $${file}.$${prefix} ]; then echo $$file.$${prefix}; fi; done \
@@ -740,6 +746,6 @@ echo-git-rev:
 -include kernel/*.d
 -include techlibs/*/*.d
 
-.PHONY: all top-all abc test install install-abc manual clean mrproper qtcreator
+.PHONY: all top-all abc test install install-abc manual clean mrproper qtcreator coverage vcxsrc mxebin
 .PHONY: config-clean config-clang config-gcc config-gcc-static config-gcc-4.8 config-gprof config-sudo
 
diff --git a/frontends/ilang/.gitignore b/frontends/ilang/.gitignore
index 43106a814..f586b33c7 100644
--- a/frontends/ilang/.gitignore
+++ b/frontends/ilang/.gitignore
@@ -1,4 +1,4 @@
 ilang_lexer.cc
 ilang_parser.output
 ilang_parser.tab.cc
-ilang_parser.tab.h
+ilang_parser.tab.hh
diff --git a/frontends/ilang/Makefile.inc b/frontends/ilang/Makefile.inc
index e2a476c93..6f1f0e8fc 100644
--- a/frontends/ilang/Makefile.inc
+++ b/frontends/ilang/Makefile.inc
@@ -1,15 +1,14 @@
 
 GENFILES += frontends/ilang/ilang_parser.tab.cc
-GENFILES += frontends/ilang/ilang_parser.tab.h
+GENFILES += frontends/ilang/ilang_parser.tab.hh
 GENFILES += frontends/ilang/ilang_parser.output
 GENFILES += frontends/ilang/ilang_lexer.cc
 
 frontends/ilang/ilang_parser.tab.cc: frontends/ilang/ilang_parser.y
 	$(Q) mkdir -p $(dir $@)
-	$(P) $(BISON) -d -r all -b frontends/ilang/ilang_parser $<
-	$(Q) mv frontends/ilang/ilang_parser.tab.c frontends/ilang/ilang_parser.tab.cc
+	$(P) $(BISON) -o $@ -d -r all -b frontends/ilang/ilang_parser $<
 
-frontends/ilang/ilang_parser.tab.h: frontends/ilang/ilang_parser.tab.cc
+frontends/ilang/ilang_parser.tab.hh: frontends/ilang/ilang_parser.tab.cc
 
 frontends/ilang/ilang_lexer.cc: frontends/ilang/ilang_lexer.l
 	$(Q) mkdir -p $(dir $@)
diff --git a/frontends/ilang/ilang_lexer.l b/frontends/ilang/ilang_lexer.l
index 842388548..d8e01ae4d 100644
--- a/frontends/ilang/ilang_lexer.l
+++ b/frontends/ilang/ilang_lexer.l
@@ -30,7 +30,7 @@
 #endif
 
 #include "frontends/ilang/ilang_frontend.h"
-#include "ilang_parser.tab.h"
+#include "ilang_parser.tab.hh"
 
 USING_YOSYS_NAMESPACE
 
diff --git a/frontends/verilog/.gitignore b/frontends/verilog/.gitignore
index 1d4ae9e5c..aadbcdcdd 100644
--- a/frontends/verilog/.gitignore
+++ b/frontends/verilog/.gitignore
@@ -1,4 +1,4 @@
 verilog_lexer.cc
 verilog_parser.output
 verilog_parser.tab.cc
-verilog_parser.tab.h
+verilog_parser.tab.hh
diff --git a/frontends/verilog/Makefile.inc b/frontends/verilog/Makefile.inc
index a06c1d5ab..dbaace585 100644
--- a/frontends/verilog/Makefile.inc
+++ b/frontends/verilog/Makefile.inc
@@ -1,15 +1,14 @@
 
 GENFILES += frontends/verilog/verilog_parser.tab.cc
-GENFILES += frontends/verilog/verilog_parser.tab.h
+GENFILES += frontends/verilog/verilog_parser.tab.hh
 GENFILES += frontends/verilog/verilog_parser.output
 GENFILES += frontends/verilog/verilog_lexer.cc
 
 frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y
 	$(Q) mkdir -p $(dir $@)
-	$(P) $(BISON) -d -r all -b frontends/verilog/verilog_parser $<
-	$(Q) mv frontends/verilog/verilog_parser.tab.c frontends/verilog/verilog_parser.tab.cc
+	$(P) $(BISON) -o $@ -d -r all -b frontends/verilog/verilog_parser $<
 
-frontends/verilog/verilog_parser.tab.h: frontends/verilog/verilog_parser.tab.cc
+frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc
 
 frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l
 	$(Q) mkdir -p $(dir $@)
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 0134416c1..83921bf0b 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -42,7 +42,7 @@
 #include "kernel/log.h"
 #include "frontends/verilog/verilog_frontend.h"
 #include "frontends/ast/ast.h"
-#include "verilog_parser.tab.h"
+#include "verilog_parser.tab.hh"
 
 USING_YOSYS_NAMESPACE
 using namespace AST;

From 380c6f0e978869099d5b2c5dd81d8065a1f5c3cc Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Mon, 27 Aug 2018 10:18:33 -0700
Subject: [PATCH 18/35] Remove unused functions.

---
 backends/firrtl/firrtl.cc | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 14fae1a83..94236d0b1 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -28,7 +28,6 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-bool defparam, noattr;
 pool<string> used_names;
 dict<IdString, string> namecache;
 int autoid_counter;
@@ -173,17 +172,8 @@ struct FirrtlWorker
 
 	void process_instance(RTLIL::Cell *cell, vector<string> &wire_exprs)
 	{
-		// TODO: Deal with cell attributes
-		if (!noattr && !cell->attributes.empty()) {
-
-		}
 		std::string cell_type = fid(cell->type);
 
-		// TODO: Deal with cell parameters
-		if (!defparam && cell->parameters.size() > 0) {
-
-		}
-
 		std::string cell_name = cellname(cell);
 		std::string cell_name_comment;
 		if (cell_name != fid(cell->name))

From 92896a58beb66d633f787c30ec291f6be8d9e0e0 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 28 Aug 2018 13:11:41 +0200
Subject: [PATCH 19/35] Remove mercurial, since it is not needed anymore

---
 .travis.yml | 5 -----
 Brewfile    | 1 -
 2 files changed, 6 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index fbb4018af..321c3325f 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -28,7 +28,6 @@ matrix:
             - tcl-dev
             - libffi-dev
             - git
-            - mercurial
             - graphviz
             - xdot
             - pkg-config
@@ -53,7 +52,6 @@ matrix:
             - tcl-dev
             - libffi-dev
             - git
-            - mercurial
             - graphviz
             - xdot
             - pkg-config
@@ -78,7 +76,6 @@ matrix:
             - tcl-dev
             - libffi-dev
             - git
-            - mercurial
             - graphviz
             - xdot
             - pkg-config
@@ -104,7 +101,6 @@ matrix:
             - tcl-dev
             - libffi-dev
             - git
-            - mercurial
             - graphviz
             - xdot
             - pkg-config
@@ -129,7 +125,6 @@ matrix:
             - tcl-dev
             - libffi-dev
             - git
-            - mercurial
             - graphviz
             - xdot
             - pkg-config
diff --git a/Brewfile b/Brewfile
index d7cd05bf1..0c58ce161 100644
--- a/Brewfile
+++ b/Brewfile
@@ -3,7 +3,6 @@ brew "flex"
 brew "gawk"
 brew "libffi"
 brew "git"
-brew "mercurial"
 brew "graphviz"
 brew "pkg-config"
 brew "python3"

From d36d11936f6725b9fc0702e9406bc55533d8e273 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Miodrag=20Milanovi=C4=87?= <mmicko@gmail.com>
Date: Tue, 28 Aug 2018 08:17:33 -0700
Subject: [PATCH 20/35] Add GCC to osx deps (#620)

* Add GCC to osx deps

* Force gcc-7 install
---
 .travis/setup.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.travis/setup.sh b/.travis/setup.sh
index 81ff37742..068515786 100755
--- a/.travis/setup.sh
+++ b/.travis/setup.sh
@@ -64,7 +64,7 @@ if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then
 		brew tap Homebrew/bundle
 		brew bundle
 		brew install ccache
-		brew install gcc
+		brew install gcc@7
 		echo
 		echo -en 'travis_fold:end:before_install.brew\\r'
 		echo

From 0b7a18470bbd35214fdeff204f9c20964e69b5c5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 30 Aug 2018 12:26:26 +0200
Subject: [PATCH 21/35] Add "make ystests"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 .gitignore   | 1 +
 CodingReadme | 1 +
 Makefile     | 8 ++++++++
 3 files changed, 10 insertions(+)

diff --git a/.gitignore b/.gitignore
index 4fce690ec..48ce458c7 100644
--- a/.gitignore
+++ b/.gitignore
@@ -34,3 +34,4 @@
 /libyosys.so
 /tests/unit/bintest/
 /tests/unit/objtest/
+/tests/ystests
diff --git a/CodingReadme b/CodingReadme
index 4ab132a63..b64e79178 100644
--- a/CodingReadme
+++ b/CodingReadme
@@ -373,6 +373,7 @@ Finally run all tests with "make config-{clang,gcc,gcc-4.8}":
 	cd ~yosys
 	make clean
 	make test
+	make ystests
 	make vloghtb
 	make install
 
diff --git a/Makefile b/Makefile
index 39a361a5f..7698047ec 100644
--- a/Makefile
+++ b/Makefile
@@ -585,6 +585,14 @@ vloghtb: $(TARGETS) $(EXTRA_TARGETS)
 	@echo "  Passed \"make vloghtb\"."
 	@echo ""
 
+ystests: $(TARGETS) $(EXTRA_TARGETS)
+	rm -rf tests/ystests
+	git clone https://github.com/YosysHQ/yosys-tests.git tests/ystests
+	+PATH="$$PWD:$$PATH" cd tests/ystests && $(MAKE)
+	@echo ""
+	@echo "  Finished \"make ystests\"."
+	@echo ""
+
 # Unit test
 unit-test: libyosys.so
 	@$(MAKE) -C $(UNITESTPATH) CXX="$(CXX)" CPPFLAGS="$(CPPFLAGS)" \

From 5d9d22f66d512d33b2c1a13c4f1a20f944e6acc3 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 4 Sep 2018 20:06:10 +0200
Subject: [PATCH 22/35] Add "verific -L <int>" option

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc    | 11 +++++++++++
 frontends/verific/verific.h     |  2 ++
 frontends/verific/verificsva.cc |  5 +++--
 3 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 1dd6d7e24..c5fa58313 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -64,6 +64,7 @@ YOSYS_NAMESPACE_BEGIN
 int verific_verbose;
 bool verific_import_pending;
 string verific_error_msg;
+int verific_sva_fsm_limit;
 
 vector<string> verific_incdirs, verific_libdirs;
 
@@ -1618,6 +1619,8 @@ struct VerificExtNets
 
 void verific_import(Design *design, std::string top)
 {
+	verific_sva_fsm_limit = 16;
+
 	std::set<Netlist*> nl_todo, nl_done;
 
 	{
@@ -1789,6 +1792,9 @@ struct VerificPass : public Pass {
 		log("  -nosva\n");
 		log("    Ignore SVA properties, do not infer checker logic.\n");
 		log("\n");
+		log("  -L <int>\n");
+		log("    Maximum number of ctrl bits for SVA checker FSMs (default=16).\n");
+		log("\n");
 		log("  -n\n");
 		log("    Keep all Verific names on instances and nets. By default only\n");
 		log("    user-declared names are preserved.\n");
@@ -1830,6 +1836,7 @@ struct VerificPass : public Pass {
 		}
 
 		verific_verbose = 0;
+		verific_sva_fsm_limit = 16;
 
 		const char *release_str = Message::ReleaseString();
 		time_t release_time = Message::ReleaseDate();
@@ -2036,6 +2043,10 @@ struct VerificPass : public Pass {
 					mode_nosva = true;
 					continue;
 				}
+				if (args[argidx] == "-L" && argidx+1 < GetSize(args)) {
+					verific_sva_fsm_limit = atoi(args[++argidx].c_str());
+					continue;
+				}
 				if (args[argidx] == "-n") {
 					mode_names = true;
 					continue;
diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h
index cbd9314db..334a436af 100644
--- a/frontends/verific/verific.h
+++ b/frontends/verific/verific.h
@@ -101,6 +101,8 @@ void verific_import_sva_cover(VerificImporter *importer, Verific::Instance *inst
 void verific_import_sva_trigger(VerificImporter *importer, Verific::Instance *inst);
 bool verific_is_sva_net(VerificImporter *importer, Verific::Net *net);
 
+extern int verific_sva_fsm_limit;
+
 YOSYS_NAMESPACE_END
 
 #endif
diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc
index 85b842186..cdc9ece8c 100644
--- a/frontends/verific/verificsva.cc
+++ b/frontends/verific/verificsva.cc
@@ -466,13 +466,14 @@ struct SvaFsm
 
 		dnode.ctrl.sort_and_unify();
 
-		if (GetSize(dnode.ctrl) > 16) {
+		if (GetSize(dnode.ctrl) > verific_sva_fsm_limit) {
 			if (verific_verbose >= 2) {
 				log("    detected state explosion in DFSM generation:\n");
 				dump();
 				log("      ctrl signal: %s\n", log_signal(dnode.ctrl));
 			}
-			log_error("SVA DFSM state ctrl signal has %d (>16) bits. Stopping to prevent exponential design size explosion.\n", GetSize(dnode.ctrl));
+			log_error("SVA DFSM state ctrl signal has %d (>%d) bits. Stopping to prevent exponential design size explosion.\n",
+					GetSize(dnode.ctrl), verific_sva_fsm_limit);
 		}
 
 		for (int i = 0; i < (1 << GetSize(dnode.ctrl)); i++)

From 12440fcc8f705c117b5f91fae24b7e5c4fbf8560 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 6 Sep 2018 00:18:01 +0200
Subject: [PATCH 23/35] Add $lut support to Verilog back-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 44e4e5f97..d3262ec47 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -779,6 +779,19 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
+	if (cell->type == "$lut")
+	{
+		f << stringf("%s" "assign ", indent.c_str());
+		dump_sigspec(f, cell->getPort("\\Y"));
+		f << stringf(" = ");
+		dump_const(f, cell->parameters.at("\\LUT"));
+		f << stringf(" >> ");
+		dump_attributes(f, "", cell->attributes, ' ');
+		dump_sigspec(f, cell->getPort("\\A"));
+		f << stringf(";\n");
+		return true;
+	}
+
 	if (cell->type == "$dffsr")
 	{
 		SigSpec sig_clk = cell->getPort("\\CLK");

From 51f1bbeeb08020a9b739d2bd0cf4d79ca6e62015 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 10 Sep 2018 11:57:24 +0200
Subject: [PATCH 24/35] Add iCE40 SB_SPRAM256KA simulation model

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/ice40/cells_sim.v | 39 +++++++++++++++++++++++++++++---------
 1 file changed, 30 insertions(+), 9 deletions(-)

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 9f73aeb07..e0a07af32 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -920,19 +920,40 @@ parameter A_SIGNED = 1'b0;
 parameter B_SIGNED = 1'b0;
 endmodule
 
-(* blackbox *)
-module SB_SPRAM256KA(
+module SB_SPRAM256KA (
 	input [13:0] ADDRESS,
 	input [15:0] DATAIN,
 	input [3:0] MASKWREN,
-	input WREN,
-	input CHIPSELECT,
-	input CLOCK,
-	input STANDBY,
-	input SLEEP,
-	input POWEROFF,
-	output [15:0] DATAOUT
+	input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
+	output reg [15:0] DATAOUT
 );
+`ifndef BLACKBOX
+	reg [15:0] mem [0:16383];
+	wire off = SLEEP || !POWEROFF;
+	integer i;
+
+	always @(negedge POWEROFF) begin
+		for (i = 0; i <= 16383; i = i+1)
+			mem[i] = 'bx;
+	end
+
+	always @(posedge CLOCK, posedge off) begin
+		if (off) begin
+			DATAOUT <= 0;
+		end else
+		if (CHIPSELECT && !STANDBY && !WREN) begin
+			DATAOUT <= mem[ADDRESS];
+		end else begin
+			if (CHIPSELECT && !STANDBY && WREN) begin
+				if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0];
+				if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4];
+				if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8];
+				if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12];
+			end
+			DATAOUT <= 'bx;
+		end
+	end
+`endif
 endmodule
 
 (* blackbox *)

From 5fe16c25b81d507fa41381eca70c5aada59db25f Mon Sep 17 00:00:00 2001
From: acw1251 <acwright@mit.edu>
Date: Wed, 12 Sep 2018 18:33:27 -0400
Subject: [PATCH 25/35] Fixed minor typo in "sim" help message

---
 passes/sat/sim.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index fadffcdbc..53e248adf 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -778,7 +778,7 @@ struct SimPass : public Pass {
 		log("        number of cycles to simulate (default: 20)\n");
 		log("\n");
 		log("    -a\n");
-		log("        include all nets in VCD output, nut just those with public names\n");
+		log("        include all nets in VCD output, not just those with public names\n");
 		log("\n");
 		log("    -w\n");
 		log("        writeback mode: use final simulation state as new init state\n");

From efac8a45a6965bdcbb7fb810d657d2c63b6cb7fe Mon Sep 17 00:00:00 2001
From: acw1251 <acwright@mit.edu>
Date: Tue, 18 Sep 2018 13:34:30 -0400
Subject: [PATCH 26/35] Fixed typo in "verilog_write" help message

---
 backends/verilog/verilog_backend.cc | 6 +++---
 manual/command-reference-manual.tex | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index d3262ec47..ae9031510 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1523,7 +1523,7 @@ struct VerilogBackend : public Backend {
 		log("\n");
 		log("    -nodec\n");
 		log("        32-bit constant values are by default dumped as decimal numbers,\n");
-		log("        not bit pattern. This option decativates this feature and instead\n");
+		log("        not bit pattern. This option deactivates this feature and instead\n");
 		log("        will write out all constants in binary.\n");
 		log("\n");
 		log("    -decimal\n");
@@ -1531,13 +1531,13 @@ struct VerilogBackend : public Backend {
 		log("\n");
 		log("    -nohex\n");
 		log("        constant values that are compatible with hex output are usually\n");
-		log("        dumped as hex values. This option decativates this feature and\n");
+		log("        dumped as hex values. This option deactivates this feature and\n");
 		log("        instead will write out all constants in binary.\n");
 		log("\n");
 		log("    -nostr\n");
 		log("        Parameters and attributes that are specified as strings in the\n");
 		log("        original input will be output as strings by this back-end. This\n");
-		log("        decativates this feature and instead will write string constants\n");
+		log("        deactivates this feature and instead will write string constants\n");
 		log("        as binary numbers.\n");
 		log("\n");
 		log("    -defparam\n");
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex
index 8af8ccdd0..fea2354e6 100644
--- a/manual/command-reference-manual.tex
+++ b/manual/command-reference-manual.tex
@@ -4421,13 +4421,13 @@ Write the current design to a Verilog file.
 
     -nodec
         32-bit constant values are by default dumped as decimal numbers,
-        not bit pattern. This option decativates this feature and instead
+        not bit pattern. This option deactivates this feature and instead
         will write out all constants in binary.
 
     -nostr
         Parameters and attributes that are specified as strings in the
         original input will be output as strings by this back-end. This
-        decativates this feature and instead will write string constants
+        deactivates this feature and instead will write string constants
         as binary numbers.
 
     -defparam

From c5e9034834ce0bcc6f6c611bc3ad3d244a32732f Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 19 Sep 2018 10:16:53 +0200
Subject: [PATCH 27/35] Fix Cygwin build and document needed packages

---
 Makefile        | 9 +++++++++
 README.md       | 4 ++++
 kernel/yosys.cc | 2 +-
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 7698047ec..365b92ea4 100644
--- a/Makefile
+++ b/Makefile
@@ -175,6 +175,12 @@ LD = gcc-4.8
 CXXFLAGS += -std=c++11 -Os
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
 
+else ifeq ($(CONFIG),cygwin)
+CXX = gcc
+LD = gcc
+CXXFLAGS += -std=gnu++11 -Os
+ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
+
 else ifeq ($(CONFIG),emcc)
 CXX = emcc
 LD = emcc
@@ -729,6 +735,9 @@ config-msys2: clean
 config-msys2-64: clean
 	echo 'CONFIG := msys2-64' > Makefile.conf
 
+config-cygwin: clean
+	echo 'CONFIG := cygwin' > Makefile.conf
+
 config-gcov: clean
 	echo 'CONFIG := gcc' > Makefile.conf
 	echo 'ENABLE_GCOV := 1' >> Makefile.conf
diff --git a/README.md b/README.md
index 424d9bbf2..41ae4ac18 100644
--- a/README.md
+++ b/README.md
@@ -69,6 +69,10 @@ On FreeBSD use the following command to install all prerequisites:
 On FreeBSD system use gmake instead of make. To run tests use:
     % MAKE=gmake CC=cc gmake test
 
+For Cygwin use the following command to install all prerequisites, or select these additional packages:
+
+	setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel
+
 There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
 as a source distribution for Visual Studio. Visit the Yosys download page for
 more information: http://www.clifford.at/yosys/download.html
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 264b1f63d..ad032899c 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -166,7 +166,7 @@ std::string vstringf(const char *fmt, va_list ap)
 	std::string string;
 	char *str = NULL;
 
-#ifdef _WIN32
+#if defined(_WIN32 )|| defined(__CYGWIN__) 
 	int sz = 64, rc;
 	while (1) {
 		va_list apc;

From bf189122a8d73f071c003a4035986cc37e2d4a31 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 21 Sep 2018 13:55:20 +0200
Subject: [PATCH 28/35] Update Changelog

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 CHANGELOG | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 54 insertions(+), 1 deletion(-)

diff --git a/CHANGELOG b/CHANGELOG
index 01c78ab3b..f09e21f89 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -3,9 +3,62 @@ List of major changes and improvements between releases
 =======================================================
 
 
-Yosys 0.7 .. Yosys ???
+Yosys 0.7 .. Yosys ???    (2017-07-07)
 ----------------------
 
+ * Various
+    - Many bugfixes and small improvements
+    - Added write_verilog hex dump support, add -nohex option
+    - Added "scc -set_attr"
+    - Added "verilog_defines" command
+    - Remeber defines from one read_verilog to next
+    - Added support for hierarchical defparam
+    - Added FIRRTL back-end
+    - Improved ABC default scripts
+    - Added "design -reset-vlog"
+    - Added "yosys -W regex" and "yosys -w regex"
+    - Added Verilog $rtoi and $itor support
+    - Added "check -initdrv"
+    - Added "read_blif -wideports"
+    - Added support for systemVerilog "++" and "--" operators
+    - Added support for SystemVerilog unique, unique0, and priority case
+    - Added "write_edif" options for edif "flavors"
+    - Added support for resetall compiler directive
+    - Added simple C beck-end (bitwise combinatorical only atm)
+    - Added $_ANDNOT_ and $_ORNOT_ cell types
+    - Added cell library aliases to "abc -g"
+    - Added "setundef -anyseq"
+    - Added "chtype" command
+    - Added "design -import"
+    - Added "write_table" command
+
+ * Changes in Yosys APIs
+    - Added ConstEval defaultval feature
+
+ * Formal Verification
+    - Added "write_aiger"
+    - Added "yosys-smtbmc --aig"
+    - Added "always <positive_int>" to .smtc format
+    - Added $cover cell type and support for cover properties
+    - Added $fair/$live cell type and support for liveness properties
+    - Added smtbmc support for memory vcd dumping
+    - Added "chformal" command
+    - Added "write_smt2 -stbv" and "write_smt2 -stdt"
+    - Fix equiv_simple, old behavior now available with "equiv_simple -short"
+    - Change to Yices2 as default SMT solver (it is GPL now)
+    - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
+
+ * Verific support
+    - Many improvements in Verific front-end
+    - Add proper handling of concurent SVA properties
+    - Map "const" and "rand const" to $anyseq/$anyconst
+
+ * GreenPAK Support
+    - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNT, etc.
+
+ * Coolrunner-II Support
+    - Added initial Coolrunner-II support
+
  * MAX10 and Cyclone IV Support
     - Added initial version of metacommand "synth_intel".
     - Improved write_verilog command to produce VQM netlist for Quartus Prime.

From 2867bf46a9265836bcdda3429f74281530c8c26d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 21 Sep 2018 16:27:07 +0200
Subject: [PATCH 29/35] Update CHANGLELOG

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 CHANGELOG | 32 +++++++++++++++++++++++++++-----
 1 file changed, 27 insertions(+), 5 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index f09e21f89..c1e93c37d 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -3,12 +3,13 @@ List of major changes and improvements between releases
 =======================================================
 
 
-Yosys 0.7 .. Yosys ???    (2017-07-07)
+Yosys 0.7 .. Yosys ???    (2017-12-12)
 ----------------------
 
  * Various
     - Many bugfixes and small improvements
     - Added write_verilog hex dump support, add -nohex option
+    - Added "write_verilog -decimal"
     - Added "scc -set_attr"
     - Added "verilog_defines" command
     - Remeber defines from one read_verilog to next
@@ -31,9 +32,20 @@ Yosys 0.7 .. Yosys ???    (2017-07-07)
     - Added "chtype" command
     - Added "design -import"
     - Added "write_table" command
+    - Added "read_json" command
+    - Added "sim" command
+    - Added "extract_fa" and "extract_reduce" commands
+    - Added "extract_counter" command
+    - Added "opt_demorgan" command
+    - Added support for $size and $bits SystemVerilog functions
+    - Added "blackbox" command
+    - Added "ltp" command
+    - Added support for editline as replacement for readline
+    - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
 
  * Changes in Yosys APIs
     - Added ConstEval defaultval feature
+    - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
 
  * Formal Verification
     - Added "write_aiger"
@@ -47,17 +59,27 @@ Yosys 0.7 .. Yosys ???    (2017-07-07)
     - Fix equiv_simple, old behavior now available with "equiv_simple -short"
     - Change to Yices2 as default SMT solver (it is GPL now)
     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
+    - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
+    - Added a brand new "write_btor" command for BTOR2
 
  * Verific support
     - Many improvements in Verific front-end
-    - Add proper handling of concurent SVA properties
+    - Added proper handling of concurent SVA properties
     - Map "const" and "rand const" to $anyseq/$anyconst
+    - Added "verific -import -flatten" and "verific -import -extnets"
+    - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
+    - Remove PSL support (because PSL has been removed in upstream Verific)
+
+ * New back-ends
+    - Added initial Coolrunner-II support
+    - Added initial eASIC support
 
  * GreenPAK Support
-    - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNT, etc.
+    - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 
- * Coolrunner-II Support
-    - Added initial Coolrunner-II support
+ * iCE40 Support
+    - Add "synth_ice40 -vpr"
+    - Add Support for UltraPlus cells
 
  * MAX10 and Cyclone IV Support
     - Added initial version of metacommand "synth_intel".

From 41affeeeb9935db73bb2774e74e6038a70cf667d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 21 Sep 2018 20:43:49 +0200
Subject: [PATCH 30/35] added prefix to FDirection constants, fixing windows
 build

---
 backends/firrtl/firrtl.cc | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 94236d0b1..32410a651 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -33,22 +33,22 @@ dict<IdString, string> namecache;
 int autoid_counter;
 
 typedef unsigned FDirection;
-static const FDirection NODIRECTION = 0x0;
-static const FDirection IN = 0x1;
-static const FDirection OUT = 0x2;
-static const FDirection INOUT = 0x3;
+static const FDirection FD_NODIRECTION = 0x0;
+static const FDirection FD_IN = 0x1;
+static const FDirection FD_OUT = 0x2;
+static const FDirection FD_INOUT = 0x3;
 
 // Get a port direction with respect to a specific module.
 FDirection getPortFDirection(IdString id, Module *module)
 {
 	Wire *wire = module->wires_.at(id);
-	FDirection direction = NODIRECTION;
+	FDirection direction = FD_NODIRECTION;
 	if (wire && wire->port_id)
 	{
 		if (wire->port_input)
-			direction |= IN;
+			direction |= FD_IN;
 		if (wire->port_output)
-			direction |= OUT;
+			direction |= FD_OUT;
 	}
 	return direction;
 }
@@ -193,16 +193,16 @@ struct FirrtlWorker
 				FDirection dir = getPortFDirection(it->first, instModule);
 				std::string source, sink;
 				switch (dir) {
-					case INOUT:
+					case FD_INOUT:
 						log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", log_id(cell_type), log_signal(it->second));
-					case OUT:
+					case FD_OUT:
 						source = firstName;
 						sink = secondName;
 						break;
-					case NODIRECTION:
+					case FD_NODIRECTION:
 						log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", log_id(cell_type), log_signal(it->second));
 						/* FALL_THROUGH */
-					case IN:
+					case FD_IN:
 						source = secondName;
 						sink = firstName;
 						break;

From 138ba7126414a3d524e7edfbbce2bdf590ac8a21 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 23 Sep 2018 09:25:40 +0200
Subject: [PATCH 31/35] Update CHANGELOG

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 CHANGELOG | 37 +++++++++++++++++++++++++++++++++++--
 1 file changed, 35 insertions(+), 2 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index c1e93c37d..5499c309a 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -3,11 +3,13 @@ List of major changes and improvements between releases
 =======================================================
 
 
-Yosys 0.7 .. Yosys ???    (2017-12-12)
+Yosys 0.7 .. Yosys 0.8
 ----------------------
 
  * Various
     - Many bugfixes and small improvements
+    - Strip debug symbols from installed binary
+    - Replace -ignore_redef with -[no]overwrite in front-ends
     - Added write_verilog hex dump support, add -nohex option
     - Added "write_verilog -decimal"
     - Added "scc -set_attr"
@@ -17,7 +19,7 @@ Yosys 0.7 .. Yosys ???    (2017-12-12)
     - Added FIRRTL back-end
     - Improved ABC default scripts
     - Added "design -reset-vlog"
-    - Added "yosys -W regex" and "yosys -w regex"
+    - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
     - Added Verilog $rtoi and $itor support
     - Added "check -initdrv"
     - Added "read_blif -wideports"
@@ -42,10 +44,25 @@ Yosys 0.7 .. Yosys ???    (2017-12-12)
     - Added "ltp" command
     - Added support for editline as replacement for readline
     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
+    - Added "yosys -E" for creating Makefile dependencies files
+    - Added "synth -noshare"
+    - Added "memory_nordff"
+    - Added "setundef -undef -expose -anyconst"
+    - Added "expose -input"
+    - Added specify/specparam parser support (simply ignore them)
+    - Added "write_blif -inames -iattr"
+    - Added "hierarchy -simcheck"
+    - Added an option to statically link abc into yosys
+    - Added protobuf back-end
+    - Added BLIF parsing support for .conn and .cname
+    - Added read_verilog error checking for reg/wire/logic misuse
+    - Added "make coverage" and ENABLE_GCOV build option
 
  * Changes in Yosys APIs
     - Added ConstEval defaultval feature
     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
+    - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
+    - Added log_file_warning() and log_file_error() functions
 
  * Formal Verification
     - Added "write_aiger"
@@ -61,6 +78,13 @@ Yosys 0.7 .. Yosys ???    (2017-12-12)
     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
     - Added a brand new "write_btor" command for BTOR2
+    - Added clk2fflogic memory support and other improvements
+    - Added "async memory write" support to write_smt2
+    - Simulate clock toggling in yosys-smtbmc VCD output
+    - Added $allseq/$allconst cells for EA-solving
+    - Make -nordff the default in "prep"
+    - Added (* gclk *) attribute
+    - Added "async2sync" pass for single-clock designs with async resets
 
  * Verific support
     - Many improvements in Verific front-end
@@ -69,16 +93,24 @@ Yosys 0.7 .. Yosys ???    (2017-12-12)
     - Added "verific -import -flatten" and "verific -import -extnets"
     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
     - Remove PSL support (because PSL has been removed in upstream Verific)
+    - Improve integration with "hierarchy" command design elaboration
+    - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
+    - Added simpilied "read" command that automatically uses verific if available
+    - Added "verific -set-<severity> <msg_id>.."
+    - Added "verific -work <libname>"
 
  * New back-ends
     - Added initial Coolrunner-II support
     - Added initial eASIC support
+    - Added initial ECP5 support
 
  * GreenPAK Support
     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 
  * iCE40 Support
     - Add "synth_ice40 -vpr"
+    - Add "synth_ice40 -nodffe"
+    - Add "synth_ice40 -json"
     - Add Support for UltraPlus cells
 
  * MAX10 and Cyclone IV Support
@@ -89,6 +121,7 @@ Yosys 0.7 .. Yosys ???    (2017-12-12)
     - Added example of implementation for DE2i-150 board.
     - Added example of implementation for MAX10 development kit.
     - Added LFSR example from Asic World.
+    - Added "dffinit -highlow" for mapping to Intel primitives
 
 
 Yosys 0.6 .. Yosys 0.7

From eb452ffb2861ceac572a4bef6dddb8db3b79deb7 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 23 Sep 2018 10:32:54 +0200
Subject: [PATCH 32/35] Added support for ommited "parameter" in Verilog-2001
 style parameter decl in SV mode

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_parser.y | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 2389d7d31..63cf646e9 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -881,9 +881,15 @@ param_decl_list:
 
 single_param_decl:
 	TOK_ID '=' expr {
-		if (astbuf1 == nullptr)
-			frontend_verilog_yyerror("syntax error");
-		AstNode *node = astbuf1->clone();
+		AstNode *node;
+		if (astbuf1 == nullptr) {
+			if (!sv_mode)
+				frontend_verilog_yyerror("syntax error");
+			node = new AstNode(AST_PARAMETER);
+			node->children.push_back(AstNode::mkconst_int(0, true));
+		} else {
+			node = astbuf1->clone();
+		}
 		node->str = *$1;
 		delete node->children[0];
 		node->children[0] = $3;

From 8fde05dfa58d87ff2e71495c77f698af19a0d80b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 24 Sep 2018 20:51:16 +0200
Subject: [PATCH 33/35] Add "read_verilog -noassert -noassume -assert-assumes"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_frontend.cc | 23 ++++++++++++++++++++++-
 frontends/verilog/verilog_frontend.h  |  9 +++++++++
 frontends/verilog/verilog_parser.y    | 23 ++++++++++++++++++-----
 3 files changed, 49 insertions(+), 6 deletions(-)

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 8dcc7c5aa..aeea36a2b 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -66,12 +66,21 @@ struct VerilogFrontend : public Frontend {
 		log("        enable support for SystemVerilog assertions and some Yosys extensions\n");
 		log("        replace the implicit -D SYNTHESIS with -D FORMAL\n");
 		log("\n");
+		log("    -noassert\n");
+		log("        ignore assert() statements\n");
+		log("\n");
+		log("    -noassume\n");
+		log("        ignore assume() statements\n");
+		log("\n");
 		log("    -norestrict\n");
-		log("        ignore restrict() assertions\n");
+		log("        ignore restrict() statements\n");
 		log("\n");
 		log("    -assume-asserts\n");
 		log("        treat all assert() statements like assume() statements\n");
 		log("\n");
+		log("    -assert-assumes\n");
+		log("        treat all assume() statements like assert() statements\n");
+		log("\n");
 		log("    -dump_ast1\n");
 		log("        dump abstract syntax tree (before simplification)\n");
 		log("\n");
@@ -229,6 +238,14 @@ struct VerilogFrontend : public Frontend {
 				formal_mode = true;
 				continue;
 			}
+			if (arg == "-noassert") {
+				noassert_mode = true;
+				continue;
+			}
+			if (arg == "-noassume") {
+				noassume_mode = true;
+				continue;
+			}
 			if (arg == "-norestrict") {
 				norestrict_mode = true;
 				continue;
@@ -237,6 +254,10 @@ struct VerilogFrontend : public Frontend {
 				assume_asserts_mode = true;
 				continue;
 			}
+			if (arg == "-assert-assumes") {
+				assert_assumes_mode = true;
+				continue;
+			}
 			if (arg == "-dump_ast1") {
 				flag_dump_ast1 = true;
 				continue;
diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h
index 16edc7985..523bbc897 100644
--- a/frontends/verilog/verilog_frontend.h
+++ b/frontends/verilog/verilog_frontend.h
@@ -54,12 +54,21 @@ namespace VERILOG_FRONTEND
 	// running in -formal mode
 	extern bool formal_mode;
 
+	// running in -noassert mode
+	extern bool noassert_mode;
+
+	// running in -noassume mode
+	extern bool noassume_mode;
+
 	// running in -norestrict mode
 	extern bool norestrict_mode;
 
 	// running in -assume-asserts mode
 	extern bool assume_asserts_mode;
 
+	// running in -assert-assumes mode
+	extern bool assert_assumes_mode;
+
 	// running in -lib mode
 	extern bool lib_mode;
 
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 63cf646e9..16cac1460 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -58,7 +58,8 @@ namespace VERILOG_FRONTEND {
 	bool do_not_require_port_stubs;
 	bool default_nettype_wire;
 	bool sv_mode, formal_mode, lib_mode;
-	bool norestrict_mode, assume_asserts_mode;
+	bool noassert_mode, noassume_mode, norestrict_mode;
+	bool assume_asserts_mode, assert_assumes_mode;
 	bool current_wire_rand, current_wire_const;
 	std::istream *lexin;
 }
@@ -1281,16 +1282,28 @@ opt_stmt_label:
 
 assert:
 	opt_stmt_label TOK_ASSERT opt_property '(' expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5));
+		if (noassert_mode)
+			delete $5;
+		else
+			ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5));
 	} |
 	opt_stmt_label TOK_ASSUME opt_property '(' expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5));
+		if (noassume_mode)
+			delete $5;
+		else
+			ast_stack.back()->children.push_back(new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5));
 	} |
 	opt_stmt_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6));
+		if (noassert_mode)
+			delete $6;
+		else
+			ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6));
 	} |
 	opt_stmt_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6));
+		if (noassume_mode)
+			delete $6;
+		else
+			ast_stack.back()->children.push_back(new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6));
 	} |
 	opt_stmt_label TOK_COVER opt_property '(' expr ')' ';' {
 		ast_stack.back()->children.push_back(new AstNode(AST_COVER, $5));

From 031824e38c737db1e47e1cde3865fd9cfd4f2a07 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 28 Sep 2018 17:20:16 +0200
Subject: [PATCH 34/35] Update to v2 YosysVS template

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 misc/create_vcxsrc.sh | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/misc/create_vcxsrc.sh b/misc/create_vcxsrc.sh
index 215e27c53..924d2722e 100644
--- a/misc/create_vcxsrc.sh
+++ b/misc/create_vcxsrc.sh
@@ -5,11 +5,11 @@ vcxsrc="$1-$2"
 yosysver="$2"
 gitsha="$3"
 
-rm -rf YosysVS-Tpl-v1.zip YosysVS
-wget http://www.clifford.at/yosys/nogit/YosysVS-Tpl-v1.zip
+rm -rf YosysVS-Tpl-v2.zip YosysVS
+wget http://www.clifford.at/yosys/nogit/YosysVS-Tpl-v2.zip
 
-unzip YosysVS-Tpl-v1.zip
-rm -f YosysVS-Tpl-v1.zip
+unzip YosysVS-Tpl-v2.zip
+rm -f YosysVS-Tpl-v2.zip
 mv YosysVS "$vcxsrc"
 
 {

From 9f9fe94b3522d465d98fa491c5992b14d268f09d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 30 Sep 2018 18:43:35 +0200
Subject: [PATCH 35/35] Fix handling of $past 2nd argument in read_verilog

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/simplify.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 04c429f7f..aa3b982d8 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1781,7 +1781,7 @@ skip_dynamic_range_lvalue_expansion:;
 				if (GetSize(children) == 2)
 				{
 					AstNode *buf = children[1]->clone();
-					while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
+					while (buf->simplify(true, false, false, stage, -1, false, false)) { }
 					if (buf->type != AST_CONSTANT)
 						log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant value.\n", str.c_str());