From 33ca6994b7870ed72cb66e865267c845b84470c9 Mon Sep 17 00:00:00 2001
From: "N. Engelhardt" <nak@yosyshq.com>
Date: Fri, 1 Dec 2023 14:28:50 +0100
Subject: [PATCH] remove example test

---
 tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v   | 77 ---------------
 tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys  |  7 --
 .../arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v  | 99 -------------------
 3 files changed, 183 deletions(-)
 delete mode 100644 tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v
 delete mode 100644 tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys
 delete mode 100644 tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v

diff --git a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v
deleted file mode 100644
index 536cce992..000000000
--- a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v
+++ /dev/null
@@ -1,77 +0,0 @@
-// Copyright 2020-2022 F4PGA Authors
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0
-
-module BRAM_TDP #(parameter AWIDTH = 10,
-parameter DWIDTH = 36)(
-	clk_a,
-	rce_a,
-	ra_a,
-	rq_a,
-	wce_a,
-	wa_a,
-	wd_a,
-
-	clk_b,
-	rce_b,
-	ra_b,
-	rq_b,
-	wce_b,
-	wa_b,
-	wd_b
-);
-
-	input                   clk_a;
-	input                   rce_a;
-	input      [AWIDTH-1:0] ra_a;
-	output reg [DWIDTH-1:0] rq_a;
-	input                   wce_a;
-	input      [AWIDTH-1:0] wa_a;
-	input      [DWIDTH-1:0] wd_a;
-
-	input                   clk_b;
-	input                   rce_b;
-	input      [AWIDTH-1:0] ra_b;
-	output reg [DWIDTH-1:0] rq_b;
-	input                   wce_b;
-	input      [AWIDTH-1:0] wa_b;
-	input      [DWIDTH-1:0] wd_b;
-
-	(* no_rw_check = 1 *)
-	reg [DWIDTH-1:0] memory[0:(1<<AWIDTH)-1];
-
-	wire [AWIDTH-1:0] a_a = rce_a ? ra_a : wa_a;
-	wire [AWIDTH-1:0] a_b = rce_b ? ra_b : wa_b;
-
-	wire ce_a = rce_a || wce_a;
-	wire ce_b = rce_b || wce_b;
-
-	always @(posedge clk_a) begin
-		if (ce_a) begin
-			if (wce_a)
-				memory[a_a] <= wd_a;
-			rq_a <= memory[a_a];
-		end
-	end
-
-	always @(posedge clk_b) begin
-		if (ce_b) begin
-			if (wce_b)
-				memory[a_b] <= wd_b;
-			rq_b <= memory[a_b];
-		end
-	end
-
-endmodule
\ No newline at end of file
diff --git a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys
deleted file mode 100644
index ccce5882f..000000000
--- a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys
+++ /dev/null
@@ -1,7 +0,0 @@
-read_verilog bram_tdp.v
-hierarchy -top BRAM_TDP
-synth_quicklogic -family qlf_k6n10f
-read_verilog -formal bram_tdp_tb.v
-read_verilog -overwrite +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
-prep -top TB
-sim -clock clk -n 20 -assert # -vcd bram_tdp.vcd
diff --git a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v
deleted file mode 100644
index 351c334d0..000000000
--- a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v
+++ /dev/null
@@ -1,99 +0,0 @@
-module TB(input clk);
-
-localparam ADDR_WIDTH = 10;
-localparam DATA_WIDTH = 36;
-localparam VECTORLEN = 16;
-
-reg rce_a_testvector [VECTORLEN-1:0];
-reg [ADDR_WIDTH-1:0] ra_a_testvector [VECTORLEN-1:0];
-reg [ADDR_WIDTH-1:0] rq_a_expected [VECTORLEN-1:0];
-
-reg wce_a_testvector [VECTORLEN-1:0];
-reg [ADDR_WIDTH-1:0] wa_a_testvector [VECTORLEN-1:0];
-reg [ADDR_WIDTH-1:0] wd_a_testvector [VECTORLEN-1:0];
-
-reg rce_b_testvector [VECTORLEN-1:0];
-reg [ADDR_WIDTH-1:0] ra_b_testvector [VECTORLEN-1:0];
-reg [ADDR_WIDTH-1:0] rq_b_expected [VECTORLEN-1:0];
-
-reg wce_b_testvector [VECTORLEN-1:0];
-reg [ADDR_WIDTH-1:0] wa_b_testvector [VECTORLEN-1:0];
-reg [ADDR_WIDTH-1:0] wd_b_testvector [VECTORLEN-1:0];
-
-reg [$clog2(VECTORLEN)-1:0] i = 0;
-
-integer j;
-initial begin
-	for (j = 0; j < VECTORLEN; j = j + 1) begin
-		rce_a_testvector[j] = 1'b0;
-		ra_a_testvector[j] = 10'h0;
-		wce_a_testvector[j] = 1'b0;
-		wa_a_testvector[j] = 10'h0;
-		rce_b_testvector[j] = 1'b0;
-		ra_b_testvector[j] = 10'h0;
-		wce_b_testvector[j] = 1'b0;
-		wa_b_testvector[j] = 10'h0;
-
-	end
-
-	wce_a_testvector[0] = 1'b1;
-	wa_a_testvector[0] = 10'hA;
-	wd_a_testvector[0] = 36'hDEADBEEF;
-
-	rce_b_testvector[2] = 1'b1;
-	ra_b_testvector[2] = 10'hA;
-	rq_b_expected[3] = 36'hDEADBEEF;
-	
-end
-
-
-wire rce_a = rce_a_testvector[i];
-wire [ADDR_WIDTH-1:0] ra_a = ra_a_testvector[i];
-wire [DATA_WIDTH-1:0] rq_a;
-
-wire wce_a = wce_a_testvector[i];
-wire [ADDR_WIDTH-1:0] wa_a = wa_a_testvector[i];
-wire [DATA_WIDTH-1:0] wd_a = wd_a_testvector[i];
-
-wire rce_b = rce_b_testvector[i];
-wire [ADDR_WIDTH-1:0] ra_b = ra_b_testvector[i];
-wire [DATA_WIDTH-1:0] rq_b;
-
-wire wce_b = wce_b_testvector[i];
-wire [ADDR_WIDTH-1:0] wa_b = wa_b_testvector[i];
-wire [DATA_WIDTH-1:0] wd_b = wd_b_testvector[i];
-
-BRAM_TDP #(
-	.AWIDTH(ADDR_WIDTH),
-	.DWIDTH(DATA_WIDTH)
-) uut (
-	.clk_a(clk),
-	.rce_a(rce_a),
-	.ra_a(ra_a),
-	.rq_a(rq_a),
-	.wce_a(wce_a),
-	.wa_a(wa_a),
-	.wd_a(wd_a),
-
-	.clk_b(clk),
-	.rce_b(rce_b),
-	.ra_b(ra_b),
-	.rq_b(rq_b),
-	.wce_b(wce_b),
-	.wa_b(wa_b),
-	.wd_b(wd_b)
-);
-
-
-always @(posedge clk) begin
-	if (i < VECTORLEN-1) begin
-		if (i > 0) begin
-			if($past(rce_a)) 
-				assert(rq_a == rq_a_expected[i]);
-			if($past(rce_b))
-				assert(rq_b == rq_b_expected[i]);
-		end
-		i <= i + 1;
-	end
-end
-endmodule
\ No newline at end of file