mirror of https://github.com/YosysHQ/yosys.git
Fixed Verilog parser fix and more similar improvements
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81d4e9e7c1
commit
33c10350b2
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@ -246,11 +246,10 @@ module_para_opt:
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'#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | /* empty */;
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'#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | /* empty */;
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module_para_list:
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module_para_list:
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single_module_para |
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single_module_para | module_para_list ',' single_module_para;
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single_module_para ',' module_para_list |
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/* empty */;
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single_module_para:
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single_module_para:
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/* empty */ |
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TOK_PARAMETER {
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TOK_PARAMETER {
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if (astbuf1) delete astbuf1;
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if (astbuf1) delete astbuf1;
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astbuf1 = new AstNode(AST_PARAMETER);
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astbuf1 = new AstNode(AST_PARAMETER);
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@ -801,14 +800,14 @@ single_cell:
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astbuf2->str = *$1;
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astbuf2->str = *$1;
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delete $1;
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delete $1;
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ast_stack.back()->children.push_back(astbuf2);
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ast_stack.back()->children.push_back(astbuf2);
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} '(' cell_port_list_opt ')' |
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} '(' cell_port_list ')' |
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TOK_ID non_opt_range {
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TOK_ID non_opt_range {
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astbuf2 = astbuf1->clone();
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astbuf2 = astbuf1->clone();
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if (astbuf2->type != AST_PRIMITIVE)
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if (astbuf2->type != AST_PRIMITIVE)
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astbuf2->str = *$1;
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astbuf2->str = *$1;
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delete $1;
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delete $1;
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ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
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ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
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} '(' cell_port_list_opt ')';
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} '(' cell_port_list ')';
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prim_list:
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prim_list:
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single_prim |
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single_prim |
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@ -819,16 +818,16 @@ single_prim:
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/* no name */ {
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/* no name */ {
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astbuf2 = astbuf1->clone();
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astbuf2 = astbuf1->clone();
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ast_stack.back()->children.push_back(astbuf2);
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ast_stack.back()->children.push_back(astbuf2);
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} '(' cell_port_list_opt ')';
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} '(' cell_port_list ')';
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cell_parameter_list_opt:
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cell_parameter_list_opt:
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'#' '(' cell_parameter_list ')' | /* empty */;
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'#' '(' cell_parameter_list ')' | /* empty */;
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cell_parameter_list:
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cell_parameter_list:
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/* empty */ | cell_parameter |
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cell_parameter | cell_parameter_list ',' cell_parameter;
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cell_parameter ',' cell_parameter_list;
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cell_parameter:
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cell_parameter:
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/* empty */ |
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expr {
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expr {
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AstNode *node = new AstNode(AST_PARASET);
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AstNode *node = new AstNode(AST_PARASET);
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astbuf1->children.push_back(node);
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astbuf1->children.push_back(node);
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@ -842,19 +841,11 @@ cell_parameter:
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delete $2;
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delete $2;
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};
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};
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cell_port_list_opt:
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/* empty */ |
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cell_port_list |
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/* empty */ ',' {
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AstNode *node = new AstNode(AST_ARGUMENT);
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astbuf2->children.push_back(node);
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} cell_port_list;
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cell_port_list:
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cell_port_list:
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cell_port |
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cell_port | cell_port_list ',' cell_port;
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cell_port_list ',' cell_port;
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cell_port:
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cell_port:
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/* empty */ |
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expr {
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expr {
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AstNode *node = new AstNode(AST_ARGUMENT);
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AstNode *node = new AstNode(AST_ARGUMENT);
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astbuf2->children.push_back(node);
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astbuf2->children.push_back(node);
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