mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #3510 from jix/ff_witness_fixes
smt2/smtbmc: Fix FF witness data for fine grained or multi chunk FFs
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commit
33a2773de0
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@ -559,6 +559,9 @@ struct Smt2Worker
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if (cell->type.in(ID($_FF_), ID($_DFF_P_), ID($_DFF_N_)))
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{
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registers.insert(cell);
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SigBit q_bit = cell->getPort(ID::Q);
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if (q_bit.is_wire())
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decls.push_back(witness_signal("reg", 1, 0, "", idcounter, q_bit.wire));
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makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(cell->getPort(ID::Q)));
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register_bool(cell->getPort(ID::Q), idcounter++);
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recursive_cells.erase(cell);
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@ -589,9 +592,12 @@ struct Smt2Worker
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if (cell->type.in(ID($ff), ID($dff)))
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{
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registers.insert(cell);
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for (auto chunk : cell->getPort(ID::Q).chunks())
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int smtoffset = 0;
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for (auto chunk : cell->getPort(ID::Q).chunks()) {
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if (chunk.is_wire())
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decls.push_back(witness_signal("reg", chunk.width, chunk.offset, "", idcounter, chunk.wire));
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decls.push_back(witness_signal("reg", chunk.width, chunk.offset, "", idcounter, chunk.wire, smtoffset));
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smtoffset += chunk.width;
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}
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makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(ID::Q)), log_signal(cell->getPort(ID::Q)));
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register_bv(cell->getPort(ID::Q), idcounter++);
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recursive_cells.erase(cell);
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@ -1490,7 +1496,7 @@ struct Smt2Worker
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return path;
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}
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std::string witness_signal(const char *type, int width, int offset, const std::string &smtname, int smtid, RTLIL::Wire *wire)
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std::string witness_signal(const char *type, int width, int offset, const std::string &smtname, int smtid, RTLIL::Wire *wire, int smtoffset = 0)
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{
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std::vector<std::string> hiername;
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const char *wire_name = wire->name.c_str();
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@ -1508,6 +1514,7 @@ struct Smt2Worker
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{ "offset", offset },
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{ "width", width },
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{ "smtname", smtname.empty() ? json11::Json(smtid) : json11::Json(smtname) },
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{ "smtoffset", smtoffset },
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{ "path", witness_path(wire) },
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}}).dump(line);
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line += "\n";
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@ -669,7 +669,7 @@ if inywfile is not None:
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if common_end <= common_offset:
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continue
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smt_expr = smt.net_expr(topmod, f"s{t}", wire["smtpath"])
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smt_expr = smt.witness_net_expr(topmod, f"s{t}", wire)
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if not smt_bool:
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slice_high = common_end - offset - 1
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@ -1267,7 +1267,8 @@ def write_yw_trace(steps_start, steps_stop, index, allregs=False):
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sigs = seqs
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for sig in sigs:
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step_values[sig["sig"]] = smt.bv2bin(smt.get(smt.net_expr(topmod, f"s{k}", sig["smtpath"])))
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value = smt.bv2bin(smt.get(smt.witness_net_expr(topmod, f"s{k}", sig)))
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step_values[sig["sig"]] = value
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yw.step(step_values)
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yw.end_trace()
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@ -958,6 +958,15 @@ class SmtIo:
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nextbase = "(|%s_h %s| %s)" % (mod, path[0], base)
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return self.net_expr(nextmod, nextbase, path[1:])
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def witness_net_expr(self, mod, base, witness):
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net = self.net_expr(mod, base, witness["smtpath"])
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is_bool = self.net_width(mod, witness["smtpath"]) == 1
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if is_bool:
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assert witness["width"] == 1
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assert witness["smtoffset"] == 0
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return net
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return "((_ extract %d %d) %s)" % (witness["smtoffset"] + witness["width"] - 1, witness["smtoffset"], net)
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def net_width(self, mod, net_path):
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for i in range(len(net_path)-1):
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assert mod in self.modinfo
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@ -4,14 +4,14 @@
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(declare-fun |smtlib2_is| (|smtlib2_s|) Bool)
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(declare-fun |smtlib2#0| (|smtlib2_s|) (_ BitVec 8)) ; \a
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; yosys-smt2-input a 8
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; yosys-smt2-witness {"offset": 0, "path": ["\\a"], "smtname": "a", "type": "input", "width": 8}
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; yosys-smt2-witness {"offset": 0, "path": ["\\a"], "smtname": "a", "smtoffset": 0, "type": "input", "width": 8}
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(define-fun |smtlib2_n a| ((state |smtlib2_s|)) (_ BitVec 8) (|smtlib2#0| state))
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(declare-fun |smtlib2#1| (|smtlib2_s|) (_ BitVec 8)) ; \b
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; yosys-smt2-input b 8
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; yosys-smt2-witness {"offset": 0, "path": ["\\b"], "smtname": "b", "type": "input", "width": 8}
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; yosys-smt2-witness {"offset": 0, "path": ["\\b"], "smtname": "b", "smtoffset": 0, "type": "input", "width": 8}
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(define-fun |smtlib2_n b| ((state |smtlib2_s|)) (_ BitVec 8) (|smtlib2#1| state))
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; yosys-smt2-output add 8
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; yosys-smt2-witness {"offset": 0, "path": ["\\add"], "smtname": "add", "type": "blackbox", "width": 8}
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; yosys-smt2-witness {"offset": 0, "path": ["\\add"], "smtname": "add", "smtoffset": 0, "type": "blackbox", "width": 8}
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(define-fun |smtlib2_n add| ((state |smtlib2_s|)) (_ BitVec 8) (let (
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(|a| (|smtlib2_n a| state))
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(|b| (|smtlib2_n b| state))
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@ -19,7 +19,7 @@
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(bvadd a b)
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))
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; yosys-smt2-output eq 1
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; yosys-smt2-witness {"offset": 0, "path": ["\\eq"], "smtname": "eq", "type": "blackbox", "width": 1}
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; yosys-smt2-witness {"offset": 0, "path": ["\\eq"], "smtname": "eq", "smtoffset": 0, "type": "blackbox", "width": 1}
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(define-fun |smtlib2_n eq| ((state |smtlib2_s|)) Bool (let (
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(|a| (|smtlib2_n a| state))
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(|b| (|smtlib2_n b| state))
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@ -27,7 +27,7 @@
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(= a b)
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))
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; yosys-smt2-output sub 8
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; yosys-smt2-witness {"offset": 0, "path": ["\\sub"], "smtname": "sub", "type": "blackbox", "width": 8}
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; yosys-smt2-witness {"offset": 0, "path": ["\\sub"], "smtname": "sub", "smtoffset": 0, "type": "blackbox", "width": 8}
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(define-fun |smtlib2_n sub| ((state |smtlib2_s|)) (_ BitVec 8) (let (
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(|a| (|smtlib2_n a| state))
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(|b| (|smtlib2_n b| state))
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@ -49,10 +49,10 @@
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(declare-fun |uut#2| (|uut_s|) (_ BitVec 8)) ; \sub
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(declare-fun |uut_h s| (|uut_s|) |smtlib2_s|)
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; yosys-smt2-anyconst uut#3 8 smtlib2_module.v:14.17-14.26
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; yosys-smt2-witness {"offset": 0, "path": ["\\a"], "smtname": 3, "type": "init", "width": 8}
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; yosys-smt2-witness {"offset": 0, "path": ["\\a"], "smtname": 3, "smtoffset": 0, "type": "init", "width": 8}
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(declare-fun |uut#3| (|uut_s|) (_ BitVec 8)) ; \a
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; yosys-smt2-anyconst uut#4 8 smtlib2_module.v:14.32-14.41
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; yosys-smt2-witness {"offset": 0, "path": ["\\b"], "smtname": 4, "type": "init", "width": 8}
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; yosys-smt2-witness {"offset": 0, "path": ["\\b"], "smtname": 4, "smtoffset": 0, "type": "init", "width": 8}
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(declare-fun |uut#4| (|uut_s|) (_ BitVec 8)) ; \b
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(define-fun |uut#5| ((state |uut_s|)) (_ BitVec 8) (bvadd (|uut#3| state) (|uut#4| state))) ; \add2
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(define-fun |uut#6| ((state |uut_s|)) Bool (= (|uut#0| state) (|uut#5| state))) ; $0$formal$smtlib2_module.v:28$1_CHECK[0:0]$9
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