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Fix handling of partial init attributes in write_verilog, fixes #997 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-05-07 19:55:36 +02:00
parent 0ee1759f00
commit 33738c1745
1 changed files with 2 additions and 1 deletions
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3
backends/verilog/verilog_backend.cc
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@ -1618,7 +1618,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
SigSpec sig = active_sigmap(wire); SigSpec sig = active_sigmap(wire);
Const val = wire->attributes.at("\\init"); Const val = wire->attributes.at("\\init");
for (int i = 0; i < GetSize(sig) && i < GetSize(val); i++) for (int i = 0; i < GetSize(sig) && i < GetSize(val); i++)
active_initdata[sig[i]] = val.bits.at(i); if (val[i] == State::S0 || val[i] == State::S1)
active_initdata[sig[i]] = val[i];
} }
if (!module->processes.empty()) if (!module->processes.empty())