mirror of https://github.com/YosysHQ/yosys.git
Revert "Do not do sign extension in techmap; let packer do it"
This reverts commit 595a8f032f
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ed303b07b7
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332b86491d
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@ -232,15 +232,24 @@ module \$__mul (A, B, Y);
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assign Y = partial_sum[n-1];
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end
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else begin
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if (A_SIGNED)
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wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);
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else
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wire [`DSP_A_MAXWIDTH-1:0] Aext = A;
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if (B_SIGNED)
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wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);
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else
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wire [`DSP_B_MAXWIDTH-1:0] Bext = B;
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`DSP_NAME #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(`MIN(Y_WIDTH,A_WIDTH+B_WIDTH)),
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.A_WIDTH(`DSP_A_MAXWIDTH),
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.B_WIDTH(`DSP_B_MAXWIDTH),
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.Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),
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) _TECHMAP_REPLACE_ (
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.A(A),
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.B(B),
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.A(Aext),
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.B(Bext),
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.Y(Y)
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);
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end
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