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Docs: Clarify verific caveats
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@ -17,12 +17,21 @@ The Yosys-Verific patch
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YosysHQ maintains and develops a patch for Verific in order to better integrate
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with Yosys and to provide features required by some of the formal verification
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front-end tools. Synthesis from RTL may be possible without this patch, however
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we are unable to provide support for any Yosys+Verific builds without it. To
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license this patch for your own Yosys builds, `contact YosysHQ`_.
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front-end tools. To license this patch for your own Yosys builds, `contact
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YosysHQ`_.
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.. warning::
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While synthesis from RTL may be possible without this patch, YosysHQ provides
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no guarantees of correctness and is unable to provide support.
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We recommend against using unpatched Yosys+Verific builds in conjunction with
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the formal verification front-end tools unless you are familiar with their inner
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workings. There are cases where the tools will appear to work, while producing
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incorrect results.
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.. note::
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Some of the formal verification front-end tools may not be fully supported
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without the full TabbyCAD suite. If you are wanting to use these tools,
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including SBY, make sure to ask us if the Yosys-Verific patch is right for
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@ -62,6 +71,10 @@ To find the compile options used for a given Yosys build, call ``yosys-config
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:start-at: --cxxflags
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:end-before: --linkflags
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.. note::
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The YosysHQ specific extensions are only available with the TabbyCAD suite.
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Required Verific features
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~~~~~~~~~~~~~~~~~~~~~~~~~
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@ -110,7 +123,7 @@ lists a series of build configurations which are possible, but only provide a
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limited subset of features. Please note that support is limited without YosysHQ
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specific extensions of Verific library.
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+--------------------------------------------------------------------------+---+---+---+-----------+
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+--------------------------------------------------------------------------+-----+-----+-----+-----+
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| | Configuration values |
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+--------------------------------------------------------------------------+-----+-----+-----+-----+
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| Features | a | b | c | d |
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