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Improvements and fixes to "bufnorm" cmd 

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
This commit is contained in:
Claire Xenia Wolf 2023-09-27 19:27:08 +02:00 committed by Martin Povišer
parent d0b5dfa6ef
commit 32808a0393
1 changed files with 37 additions and 1 deletions
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38
passes/techmap/bufnorm.cc
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@ -69,6 +69,8 @@ struct BufnormPass : public Pass {
for (auto module : design->selected_modules())
{
log("Buffer-normalizing module %s.\n", log_id(module));
SigMap sigmap(module);
module->new_connections({});
@ -112,6 +114,7 @@ struct BufnormPass : public Pass {
bit2wires[key].insert(wire);
if (wire->port_input) {
log(" primary input: %s\n", log_id(module));
for (auto bit : SigSpec(wire))
mapped_bits[sigmap(bit)] = bit;
} else {
@ -126,9 +129,14 @@ struct BufnormPass : public Pass {
if (!cell->output(conn.first))
continue;
Wire *w = conn.second.as_wire();
if (w->name.isPublic())
log(" directly driven by cell %s port %s: %s\n",
log_id(cell), log_id(conn.first), log_id(w));
for (auto bit : conn.second)
mapped_bits[sigmap(bit)] = bit;
unmapped_wires.erase(conn.second.as_wire());
unmapped_wires.erase(w);
}
}
@ -142,6 +150,8 @@ struct BufnormPass : public Pass {
unmapped_wires.sort(compareWires);
pool<Cell*> added_buffers;
for (auto wire : unmapped_wires)
{
SigSpec keysig = sigmap(wire), insig = wire, outsig = wire;
@ -150,6 +160,8 @@ struct BufnormPass : public Pass {
for (int i = 0; i < GetSize(outsig); i++)
mapped_bits[keysig[i]] = outsig[i];
log(" adding buffer for %s -> %s\n", log_signal(insig), log_signal(outsig));
if (connections_mode) {
if (bits_mode) {
for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++)
@ -164,12 +176,36 @@ struct BufnormPass : public Pass {
c->setPort(buf_inport, insig[i]);
c->setPort(buf_outport, outsig[i]);
c->fixup_parameters();
added_buffers.insert(c);
}
} else {
Cell *c = module->addCell(NEW_ID, buf_celltype);
c->setPort(buf_inport, insig);
c->setPort(buf_outport, outsig);
c->fixup_parameters();
added_buffers.insert(c);
}
}
}
for (auto cell : module->cells())
{
if (added_buffers.count(cell))
continue;
for (auto &conn : cell->connections())
{
if (cell->output(conn.first))
continue;
SigSpec newsig = conn.second;
for (auto &bit : newsig)
bit = mapped_bits[sigmap(bit)];
if (conn.second != newsig) {
log(" fixing input signal on cell %s port %s: %s\n",
log_id(cell), log_id(conn.first), log_signal(newsig));
cell->setPort(conn.first, newsig);
}
}
}