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In this directory you will find out, how to generate a spice output
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operating in two modes, analog or event-driven mode supported by ngspice
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xspice sub-module.
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Each test bench can be run separately by either running:
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- testbench.sh, to start analog simulation or
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- testbench_digital.sh for mixed-signal digital simulation.
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The later case also includes pure verilog simulation using the iverilog
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and gtkwave to represent the results.
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read_verilog counter.v
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read_verilog -lib cmos_cells.v
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proc;; memory;; techmap;;
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dfflibmap -liberty cmos_cells.lib
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abc -liberty cmos_cells.lib;;
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# http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib
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# dfflibmap -liberty osu025_stdcells.lib
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# abc -liberty osu025_stdcells.lib;;
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write_verilog synth.v
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write_spice -neg 0s -pos 1s synth.sp
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module counter_tb;
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/* Make a reset pulse and specify dump file */
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reg reset = 0;
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initial begin
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$dumpfile("counter_tb.vcd");
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$dumpvars(0,counter_tb);
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# 0 reset = 1;
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# 4 reset = 0;
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# 36 reset = 1;
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# 4 reset = 0;
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# 6 $finish;
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end
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/* Make enable with period of 8 and 6,7 low */
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reg en = 1;
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always begin
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en = 1;
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#6;
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en = 0;
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#2;
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end
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/* Make a regular pulsing clock. */
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reg clk = 0;
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always #1 clk = !clk;
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/* UUT */
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wire [2:0] count;
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counter c1 (clk, reset, en, count);
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endmodule
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#!/bin/bash
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# iverlog simulation
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echo "Doing Verilog simulation with iverilog"
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iverilog -o dsn counter.v counter_tb.v
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./dsn -lxt2
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gtkwave counter_tb.vcd &
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# yosys synthesis
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set -ex
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../../yosys counter_digital.ys
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# requires ngspice with xspice support enabled:
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ngspice testbench_digital.sp
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* supply voltages
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.global Vss Vdd
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Vss Vss 0 DC 0
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Vdd Vdd 0 DC 3
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* simple transistor model
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.MODEL cmosn NMOS LEVEL=1 VT0=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
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.MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
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* load design and library
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* load design and library
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.include cmos_cells_digital.sp
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.include cmos_cells_digital.sp
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.include synth.sp
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.include synth.sp
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