mirror of https://github.com/YosysHQ/yosys.git
abc9_map.v to do `zinit' and make INIT = 1'b0
This commit is contained in:
Eddie Hung
parent
c6ee2fb482
commit
31ef4cc704
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@ -71,43 +71,55 @@
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// state
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// (e) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
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// into the (combinatorial) FD* cell to facilitate clock-enable behaviour
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// In order to perform sequential synthesis, `abc9' also requires that
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// the initial value of all flops be zero.
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module FDRE (output reg Q, input C, CE, D, R);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_R_INVERTED = 1'b0;
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wire $nextQ;
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wire DD, QQ, $nextQ;
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generate if (INIT == 1'b1)
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assign DD = ~D, Q = ~QQ;
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else
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assign DD = D, Q = QQ;
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endgenerate
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FDRE #(
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.INIT(INIT),
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.INIT(1'b0),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_R_INVERTED(IS_R_INVERTED)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
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.D(DD), .Q($nextQ), .C(C), .CE(CE), .R(R)
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);
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
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// Special signals
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wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
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wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
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endmodule
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module FDRE_1 (output reg Q, input C, CE, D, R);
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parameter [0:0] INIT = 1'b0;
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wire $nextQ;
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wire DD, QQ, $nextQ;
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generate if (INIT == 1'b1)
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assign DD = ~D, Q = ~QQ;
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else
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assign DD = D, Q = QQ;
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endgenerate
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FDRE_1 #(
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.INIT(INIT),
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.INIT(1'b0),
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
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.D(DD), .Q($nextQ), .C(C), .CE(CE), .R(R)
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);
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
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// Special signals
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wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
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wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
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endmodule
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module FDCE (output reg Q, input C, CE, D, CLR);
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@ -115,14 +127,19 @@ module FDCE (output reg Q, input C, CE, D, CLR);
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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wire $nextQ, $abc9_currQ;
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wire DD, QQ, $nextQ, $abc9_currQ;
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generate if (INIT == 1'b1)
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assign DD = ~D, Q = ~QQ;
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else
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assign DD = D, Q = QQ;
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endgenerate
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FDCE #(
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.INIT(INIT),
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.INIT(1'b0),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_CLR_INVERTED(IS_CLR_INVERTED)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
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.D(DD), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
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// ^^^ Note that async
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// control is not directly
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// supported by abc9 but its
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@ -132,21 +149,26 @@ module FDCE (output reg Q, input C, CE, D, CLR);
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
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// Since this is an async flop, async behaviour is also dealt with
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// using the $_ABC9_ASYNC box by abc9_map.v
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\$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
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\$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
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// Special signals
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wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
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wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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endmodule
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module FDCE_1 (output reg Q, input C, CE, D, CLR);
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parameter [0:0] INIT = 1'b0;
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wire $nextQ, $abc9_currQ;
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wire DD, QQ, $nextQ, $abc9_currQ;
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generate if (INIT == 1'b1)
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assign DD = ~D, Q = ~QQ;
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else
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assign DD = D, Q = QQ;
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endgenerate
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FDCE_1 #(
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.INIT(INIT)
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.INIT(1'b0)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
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.D(DD), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
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// ^^^ Note that async
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// control is not directly
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// supported by abc9 but its
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@ -154,28 +176,33 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
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// $__ABC9_ASYNC below
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);
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
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\$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(Q));
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\$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
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// Special signals
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wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
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wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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endmodule
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module FDPE (output reg Q, input C, CE, D, PRE);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] INIT = 1'b1;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_PRE_INVERTED = 1'b0;
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wire $nextQ, $abc9_currQ;
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wire DD, QQ, $nextQ, $abc9_currQ;
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generate if (INIT == 1'b1)
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assign DD = ~D, Q = ~QQ;
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else
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assign DD = D, Q = QQ;
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endgenerate
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FDPE #(
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.INIT(INIT),
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.INIT(1'b0),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_PRE_INVERTED(IS_PRE_INVERTED),
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
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.D(DD), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
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// ^^^ Note that async
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// control is not directly
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// supported by abc9 but its
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@ -183,21 +210,26 @@ module FDPE (output reg Q, input C, CE, D, PRE);
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// $__ABC9_ASYNC below
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);
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
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\$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
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\$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
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// Special signals
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wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
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wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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endmodule
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module FDPE_1 (output reg Q, input C, CE, D, PRE);
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parameter [0:0] INIT = 1'b0;
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wire $nextQ, $abc9_currQ;
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parameter [0:0] INIT = 1'b1;
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wire DD, QQ, $nextQ, $abc9_currQ;
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generate if (INIT == 1'b1)
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assign DD = ~D, Q = ~QQ;
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else
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assign DD = D, Q = QQ;
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endgenerate
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FDPE_1 #(
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.INIT(INIT)
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.INIT(1'b0),
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
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.D(DD), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
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// ^^^ Note that async
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// control is not directly
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// supported by abc9 but its
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@ -205,13 +237,13 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
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// $__ABC9_ASYNC below
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);
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
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\$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(Q));
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\$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
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// Special signals
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wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
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wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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endmodule
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module FDSE (output reg Q, input C, CE, D, S);
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@ -219,38 +251,48 @@ module FDSE (output reg Q, input C, CE, D, S);
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_S_INVERTED = 1'b0;
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wire $nextQ;
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wire DD, QQ, $nextQ;
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generate if (INIT == 1'b1)
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assign DD = ~D, Q = ~QQ;
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else
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assign DD = D, Q = QQ;
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endgenerate
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FDSE #(
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.INIT(INIT),
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.INIT(1'b0),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_S_INVERTED(IS_S_INVERTED)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
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.D(DD), .Q($nextQ), .C(C), .CE(CE), .S(S)
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);
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
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// Special signals
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wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
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wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
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endmodule
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module FDSE_1 (output reg Q, input C, CE, D, S);
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parameter [0:0] INIT = 1'b1;
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wire $nextQ;
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wire DD, QQ, $nextQ;
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generate if (INIT == 1'b1)
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assign DD = ~D, Q = ~QQ;
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else
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assign DD = D, Q = QQ;
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endgenerate
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FDSE_1 #(
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.INIT(INIT),
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.INIT(1'b0),
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
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.D(DD), .Q($nextQ), .C(C), .CE(CE), .S(S)
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);
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
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// Special signals
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wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
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wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
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endmodule
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module RAM32X1D (
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