mirror of https://github.com/YosysHQ/yosys.git
celledges: Use b_width_capped for left shifts
`b_width_capped` already exists for preventing arithmetic overflow, limiting the value of `b_width` to 30. This just changes the left shifts to also use it. The caveat of incorrect results for extremely large values of `a_width` still applies, as does the improbability of that actually happening. This fixes #4844 (or at least, the floating point exception; the circuit still isn't valid but I think that's fine).
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@ -253,13 +253,13 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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if (a_width == 1 && is_signed) {
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int skip = 1 << (k + 1);
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int base = skip -1;
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if (i % skip != base && i - a_width + 2 < 1 << b_width)
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if (i % skip != base && i - a_width + 2 < 1 << b_width_capped)
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db->add_edge(cell, ID::B, k, ID::Y, i, -1);
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} else if (is_signed) {
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if (i - a_width + 2 < 1 << b_width)
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if (i - a_width + 2 < 1 << b_width_capped)
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db->add_edge(cell, ID::B, k, ID::Y, i, -1);
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} else {
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if (i - a_width + 1 < 1 << b_width)
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if (i - a_width + 1 < 1 << b_width_capped)
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db->add_edge(cell, ID::B, k, ID::Y, i, -1);
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}
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// right shifts
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