riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

macc_v2: Fix language constructs in simlib model

This commit is contained in:
Martin Povišer 2025-01-24 12:35:36 +01:00
parent cb8f855f34
commit 3184b335da
1 changed files with 31 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
techlibs/common/simlib.v
View File

@ -1234,22 +1234,22 @@ parameter C_SIGNED = 1'bx;
function integer sum_widths1; function integer sum_widths1;
input [(16*NPRODUCTS)-1:0] widths; input [(16*NPRODUCTS)-1:0] widths;
int i; integer i;
sum_widths1 = 0;
begin begin
sum_widths1 = 0;
for (i = 0; i < NPRODUCTS; i++) begin for (i = 0; i < NPRODUCTS; i++) begin
sum_widths1 += widths[16*i+:16]; sum_widths1 = sum_widths1 + widths[16*i+:16];
end end
end end
endfunction endfunction
function integer sum_widths2; function integer sum_widths2;
input [(16*NADDENDS)-1:0] widths; input [(16*NADDENDS)-1:0] widths;
int i; integer i;
sum_widths2 = 0;
begin begin
sum_widths2 = 0;
for (i = 0; i < NADDENDS; i++) begin for (i = 0; i < NADDENDS; i++) begin
sum_widths2 += widths[16*i+:16]; sum_widths2 = sum_widths2 + widths[16*i+:16];
end end
end end
endfunction endfunction
@ -1261,9 +1261,7 @@ output reg [Y_WIDTH-1:0] Y; // output sum
integer i, j, ai, bi, ci, aw, bw, cw; integer i, j, ai, bi, ci, aw, bw, cw;
reg [Y_WIDTH-1:0] product; reg [Y_WIDTH-1:0] product;
reg signed [Y_WIDTH-1:0] product_signed; reg [Y_WIDTH-1:0] addend, oper_a, oper_b;
reg [Y_WIDTH-1:0] addend;
reg signed [Y_WIDTH-1:0] addend_signed;
always @* begin always @* begin
Y = 0; Y = 0;
@ -1274,20 +1272,29 @@ always @* begin
aw = A_WIDTHS[16*i+:16]; aw = A_WIDTHS[16*i+:16];
bw = B_WIDTHS[16*i+:16]; bw = B_WIDTHS[16*i+:16];
product = A[ai +: aw] * B[bi +: bw]; oper_a = 0;
product_signed = $signed(A[ai +: aw]) * $signed(B[bi +: bw]); oper_b = 0;
for (j = 0; j < Y_WIDTH && j < aw; j = j + 1)
oper_a[j] = A[ai + j];
for (j = 0; j < Y_WIDTH && j < bw; j = j + 1)
oper_b[j] = B[bi + j];
// A_SIGNED[i] == B_SIGNED[i] as RTLIL invariant // A_SIGNED[i] == B_SIGNED[i] as RTLIL invariant
if (A_SIGNED[i] && B_SIGNED[i]) if (A_SIGNED[i] && B_SIGNED[i]) begin
product = product_signed; for (j = aw; j > 0 && j < Y_WIDTH; j = j + 1)
oper_a[j] = oper_a[j - 1];
for (j = bw; j > 0 && j < Y_WIDTH; j = j + 1)
oper_b[j] = oper_b[j - 1];
end
product = oper_a * oper_b;
if (PRODUCT_NEGATED[i]) if (PRODUCT_NEGATED[i])
Y = Y - product; Y = Y - product;
else else
Y = Y + product; Y = Y + product;
ai += aw; ai = ai + aw;
bi += bw; bi = bi + bw;
end end
ci = 0; ci = 0;
@ -1295,18 +1302,20 @@ always @* begin
begin begin
cw = C_WIDTHS[16*i+:16]; cw = C_WIDTHS[16*i+:16];
addend = C[ci +: cw]; addend = 0;
addend_signed = $signed(C[ci +: cw]); for (j = 0; j < Y_WIDTH && j < cw; j = j + 1)
addend[j] = C[ci + j];
if (C_SIGNED[i]) if (C_SIGNED[i]) begin
addend = addend_signed; for (j = cw; j > 0 && j < Y_WIDTH; j = j + 1)
addend[j] = addend[j - 1];
end
if (ADDEND_NEGATED[i]) if (ADDEND_NEGATED[i])
Y = Y - addend; Y = Y - addend;
else else
Y = Y + addend; Y = Y + addend;
ci += cw; ci = ci + cw;
end end
end end