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iCE40: SB_CARRY const fold -> unmap SB_LUT

This commit is contained in:
Clifford Wolf 2015-04-27 10:27:50 +02:00
parent 794d22969d
commit 310fde197e
1 changed files with 44 additions and 3 deletions
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47
techlibs/ice40/ice40_opt.cc
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@ -17,8 +17,9 @@
* *
*/ */
#include "kernel/register.h" #include "kernel/yosys.h"
#include "kernel/log.h" #include "kernel/sigtools.h"
#include "passes/techmap/simplemap.h"
#include <stdlib.h> #include <stdlib.h>
#include <stdio.h> #include <stdio.h>
@ -27,8 +28,18 @@ PRIVATE_NAMESPACE_BEGIN
static void run_ice40_opts(Module *module) static void run_ice40_opts(Module *module)
{ {
pool<SigBit> optimized_co;
vector<Cell*> sb_lut_cells;
SigMap sigmap(module);
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
{ {
if (cell->type == "\\SB_LUT4")
{
sb_lut_cells.push_back(cell);
continue;
}
if (cell->type == "\\SB_CARRY") if (cell->type == "\\SB_CARRY")
{ {
SigSpec non_const_inputs, replacement_output; SigSpec non_const_inputs, replacement_output;
@ -54,15 +65,45 @@ static void run_ice40_opts(Module *module)
replacement_output = non_const_inputs; replacement_output = non_const_inputs;
if (GetSize(replacement_output)) { if (GetSize(replacement_output)) {
optimized_co.insert(sigmap(cell->getPort("\\CO")));
module->connect(cell->getPort("\\CO"), replacement_output); module->connect(cell->getPort("\\CO"), replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true); module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized away SB_CARRY cell %s.%s: CO=%s\n", log("Optimized away SB_CARRY cell %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output)); log_id(module), log_id(cell), log_signal(replacement_output));
module->remove(cell); module->remove(cell);
continue;
} }
continue;
} }
} }
for (auto cell : sb_lut_cells)
{
if (optimized_co.count(sigmap(cell->getPort("\\I0")))) goto remap_lut;
if (optimized_co.count(sigmap(cell->getPort("\\I1")))) goto remap_lut;
if (optimized_co.count(sigmap(cell->getPort("\\I2")))) goto remap_lut;
if (optimized_co.count(sigmap(cell->getPort("\\I3")))) goto remap_lut;
continue;
remap_lut:
log("Mapping SB_LUT4 cell %s.%s back to logic.\n", log_id(module), log_id(cell));
cell->type ="$lut";
cell->setParam("\\WIDTH", 4);
cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
cell->unsetParam("\\LUT_INIT");
cell->setPort("\\A", SigSpec({cell->getPort("\\I0"), cell->getPort("\\I1"), cell->getPort("\\I2"), cell->getPort("\\I3")}));
cell->setPort("\\Y", cell->getPort("\\O"));
cell->unsetPort("\\I0");
cell->unsetPort("\\I1");
cell->unsetPort("\\I2");
cell->unsetPort("\\I3");
cell->unsetPort("\\O");
cell->check();
simplemap_lut(module, cell);
module->remove(cell);
}
} }
struct Ice40OptPass : public Pass { struct Ice40OptPass : public Pass {