mirror of https://github.com/YosysHQ/yosys.git
Fixed another bug in write_blif handling of $lut cells
This commit is contained in:
parent
36f0451ab4
commit
30de490d86
|
@ -220,7 +220,7 @@ struct BlifDumper
|
||||||
auto &inputs = cell->getPort("\\A");
|
auto &inputs = cell->getPort("\\A");
|
||||||
auto width = cell->parameters.at("\\WIDTH").as_int();
|
auto width = cell->parameters.at("\\WIDTH").as_int();
|
||||||
log_assert(inputs.size() == width);
|
log_assert(inputs.size() == width);
|
||||||
for (int i = 0; i < inputs.size(); i++) {
|
for (int i = width-1; i >= 0; i--) {
|
||||||
f << stringf(" %s", cstr(inputs.extract(i, 1)));
|
f << stringf(" %s", cstr(inputs.extract(i, 1)));
|
||||||
}
|
}
|
||||||
auto &output = cell->getPort("\\Y");
|
auto &output = cell->getPort("\\Y");
|
||||||
|
|
Loading…
Reference in New Issue