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Merge pull request #1868 from boqwxp/cleanup_delete 

Clean up `passes/cmds/delete.cc`.
This commit is contained in:
whitequark 2020-04-06 10:58:38 +00:00 committed by GitHub
parent d3615ee445 1226d41c61
commit 30934e425d
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 19 additions and 24 deletions
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43
passes/cmds/delete.cc
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@ -65,27 +65,24 @@ struct DeletePass : public Pass {
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
std::vector<RTLIL::IdString> delete_mods; std::vector<RTLIL::Module *> delete_mods;
for (auto module : design->modules())
for (auto &mod_it : design->modules_)
{ {
if (design->selected_whole_module(mod_it.first) && !flag_input && !flag_output) { if (design->selected_whole_module(module->name) && !flag_input && !flag_output) {
delete_mods.push_back(mod_it.first); delete_mods.push_back(module);
continue; continue;
} }
if (!design->selected_module(mod_it.first)) if (!design->selected_module(module->name))
continue; continue;
RTLIL::Module *module = mod_it.second;
if (flag_input || flag_output) { if (flag_input || flag_output) {
for (auto &it : module->wires_) for (auto wire : module->wires())
if (design->selected(module, it.second)) { if (design->selected(module, wire)) {
if (flag_input) if (flag_input)
it.second->port_input = false; wire->port_input = false;
if (flag_output) if (flag_output)
it.second->port_output = false; wire->port_output = false;
} }
module->fixup_ports(); module->fixup_ports();
continue; continue;
@ -96,20 +93,19 @@ struct DeletePass : public Pass {
pool<RTLIL::IdString> delete_procs; pool<RTLIL::IdString> delete_procs;
pool<RTLIL::IdString> delete_mems; pool<RTLIL::IdString> delete_mems;
for (auto &it : module->wires_) for (auto wire : module->selected_wires())
if (design->selected(module, it.second)) delete_wires.insert(wire);
delete_wires.insert(it.second);
for (auto &it : module->memories) for (auto &it : module->memories)
if (design->selected(module, it.second)) if (design->selected(module, it.second))
delete_mems.insert(it.first); delete_mems.insert(it.first);
for (auto &it : module->cells_) { for (auto cell : module->cells()) {
if (design->selected(module, it.second)) if (design->selected(module, cell))
delete_cells.insert(it.second); delete_cells.insert(cell);
if (it.second->type.in(ID($memrd), ID($memwr)) && if (cell->type.in(ID($memrd), ID($memwr)) &&
delete_mems.count(it.second->parameters.at(ID::MEMID).decode_string()) != 0) delete_mems.count(cell->parameters.at(ID::MEMID).decode_string()) != 0)
delete_cells.insert(it.second); delete_cells.insert(cell);
} }
for (auto &it : module->processes) for (auto &it : module->processes)
@ -134,9 +130,8 @@ struct DeletePass : public Pass {
module->fixup_ports(); module->fixup_ports();
} }
for (auto &it : delete_mods) { for (auto mod : delete_mods) {
delete design->modules_.at(it); design->remove(mod);
design->modules_.erase(it);
} }
} }
} DeletePass; } DeletePass;