mirror of https://github.com/YosysHQ/yosys.git
Run "clean -purge" on holes_module in its own design
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5545cd3c10
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3090da2d98
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@ -621,8 +621,7 @@ struct XAigerWriter
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log_debug("boxNum = %d\n", GetSize(box_list));
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log_debug("boxNum = %d\n", GetSize(box_list));
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write_h_buffer(box_list.size());
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write_h_buffer(box_list.size());
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RTLIL::Module *holes_module = nullptr;
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RTLIL::Module *holes_module = module->design->addModule("$__holes__");
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holes_module = module->design->addModule("$__holes__");
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log_assert(holes_module);
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log_assert(holes_module);
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int port_id = 1;
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int port_id = 1;
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@ -726,20 +725,26 @@ struct XAigerWriter
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if (!cell->type.in("$_NOT_", "$_AND_"))
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if (!cell->type.in("$_NOT_", "$_AND_"))
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log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
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log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
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Pass::call(holes_module->design, "clean -purge");
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holes_module->design->selection_stack.pop_back();
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// Move into a new (temporary) design so that "clean" will only
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// operate (and run checks on) this one module
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RTLIL::Design *holes_design = new RTLIL::Design;
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holes_module->design->modules_.erase(holes_module->name);
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holes_design->add(holes_module);
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Pass::call(holes_design, "clean -purge");
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std::stringstream a_buffer;
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std::stringstream a_buffer;
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XAigerWriter writer(holes_module, true /* holes_mode */);
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XAigerWriter writer(holes_module, true /* holes_mode */);
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writer.write_aiger(a_buffer, false /*ascii_mode*/);
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writer.write_aiger(a_buffer, false /*ascii_mode*/);
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holes_module->design->selection_stack.pop_back();
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delete holes_design;
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f << "a";
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f << "a";
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std::string buffer_str = a_buffer.str();
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std::string buffer_str = a_buffer.str();
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int32_t buffer_size_be = to_big_endian(buffer_str.size());
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int32_t buffer_size_be = to_big_endian(buffer_str.size());
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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f.write(buffer_str.data(), buffer_str.size());
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holes_module->design->remove(holes_module);
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log_pop();
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log_pop();
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}
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}
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