From c3145863e7a815f60b62b8d015506672ccdbcd89 Mon Sep 17 00:00:00 2001
From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Mon, 28 Aug 2017 09:06:37 -0700
Subject: [PATCH 1/5] Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking
 that they're multi-edge-sensitive and getting confused.

---
 techlibs/greenpak4/cells_sim_digital.v | 72 +++++++++++++-------------
 1 file changed, 36 insertions(+), 36 deletions(-)

diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
index 043cd18d4..b87795ceb 100644
--- a/techlibs/greenpak4/cells_sim_digital.v
+++ b/techlibs/greenpak4/cells_sim_digital.v
@@ -147,7 +147,15 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 			"RISING": begin
 				always @(posedge CLK, posedge RST) begin
 
-					if(KEEP) begin
+					//Resets
+					if(RST) begin
+						if(RESET_VALUE == "ZERO")
+							count	<= 0;
+						else
+							count	<= COUNT_TO;
+					end
+
+					else if(KEEP) begin
 					end
 					else if(UP) begin
 						count		<= count + 1'd1;
@@ -161,21 +169,21 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 							count	<= COUNT_TO;
 					end
 
-					//Resets
-					if(RST) begin
-						if(RESET_VALUE == "ZERO")
-							count	<= 0;
-						else
-							count	<= COUNT_TO;
-					end
-
 				end
 			end
 
 			"FALLING": begin
 				always @(posedge CLK, negedge RST) begin
 
-					if(KEEP) begin
+					//Resets
+					if(!RST) begin
+						if(RESET_VALUE == "ZERO")
+							count	<= 0;
+						else
+							count	<= COUNT_TO;
+					end
+
+					else if(KEEP) begin
 					end
 					else if(UP) begin
 						count		<= count + 1'd1;
@@ -189,14 +197,6 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 							count	<= COUNT_TO;
 					end
 
-					//Resets
-					if(!RST) begin
-						if(RESET_VALUE == "ZERO")
-							count	<= 0;
-						else
-							count	<= COUNT_TO;
-					end
-
 				end
 			end
 
@@ -286,8 +286,16 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 			"RISING": begin
 				always @(posedge CLK, posedge RST) begin
 
+					//Resets
+					if(RST) begin
+						if(RESET_VALUE == "ZERO")
+							count	<= 0;
+						else
+							count	<= COUNT_TO;
+					end
+
 					//Main counter
-					if(KEEP) begin
+					else if(KEEP) begin
 					end
 					else if(UP) begin
 						count		<= count + 1'd1;
@@ -301,22 +309,22 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 							count	<= COUNT_TO;
 					end
 
-					//Resets
-					if(RST) begin
-						if(RESET_VALUE == "ZERO")
-							count	<= 0;
-						else
-							count	<= COUNT_TO;
-					end
-
 				end
 			end
 
 			"FALLING": begin
 				always @(posedge CLK, negedge RST) begin
 
+					//Resets
+					if(!RST) begin
+						if(RESET_VALUE == "ZERO")
+							count	<= 0;
+						else
+							count	<= COUNT_TO;
+					end
+
 					//Main counter
-					if(KEEP) begin
+					else if(KEEP) begin
 					end
 					else if(UP) begin
 						count		<= count + 1'd1;
@@ -330,14 +338,6 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 							count	<= COUNT_TO;
 					end
 
-					//Resets
-					if(!RST) begin
-						if(RESET_VALUE == "ZERO")
-							count	<= 0;
-						else
-							count	<= COUNT_TO;
-					end
-
 				end
 			end
 

From 32c0f1193e3fffdfed2fc99d48f05772661a4051 Mon Sep 17 00:00:00 2001
From: Jason Lowdermilk <jlowder@chipscan.us>
Date: Tue, 29 Aug 2017 14:46:35 -0600
Subject: [PATCH 2/5] Add support for source line tracking through synthesis
 phase

---
 kernel/rtlil.cc             |  7 ++++---
 kernel/rtlil.h              | 36 ++++++++++++++++++------------------
 passes/techmap/alumacc.cc   | 16 ++++++++++++----
 passes/techmap/dfflibmap.cc |  4 ++++
 passes/techmap/techmap.cc   |  7 +++++++
 5 files changed, 45 insertions(+), 25 deletions(-)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 4427303cc..f132d299b 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1620,18 +1620,19 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth
 }
 
 #define DEF_METHOD(_func, _y_size, _type) \
-	RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
+		RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, std::string src) { \
 		RTLIL::Cell *cell = addCell(name, _type);           \
 		cell->parameters["\\A_SIGNED"] = is_signed;         \
 		cell->parameters["\\A_WIDTH"] = sig_a.size();       \
 		cell->parameters["\\Y_WIDTH"] = sig_y.size();       \
 		cell->setPort("\\A", sig_a);                        \
 		cell->setPort("\\Y", sig_y);                        \
+		if (!src.empty()) cell->attributes["\\src"] = src;  \
 		return cell;                                        \
 	} \
-	RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
+		RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, std::string src) { \
 		RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size);    \
-		add ## _func(name, sig_a, sig_y, is_signed);        \
+		add ## _func(name, sig_a, sig_y, is_signed, src);   \
 		return sig_y;                                       \
 	}
 DEF_METHOD(Not,        sig_a.size(), "$not")
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index be558932f..2769d895f 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -960,20 +960,20 @@ public:
 
 	// The add* methods create a cell and return the created cell. All signals must exist in advance.
 
-	RTLIL::Cell* addNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
-	RTLIL::Cell* addPos (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
-	RTLIL::Cell* addNeg (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
+	RTLIL::Cell* addNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, std::string src = "");
+	RTLIL::Cell* addPos (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, std::string src = "");
+	RTLIL::Cell* addNeg (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, std::string src = "");
 
 	RTLIL::Cell* addAnd  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addOr   (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addXor  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addXnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 
-	RTLIL::Cell* addReduceAnd  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
-	RTLIL::Cell* addReduceOr   (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
-	RTLIL::Cell* addReduceXor  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
-	RTLIL::Cell* addReduceXnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
-	RTLIL::Cell* addReduceBool (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
+	RTLIL::Cell* addReduceAnd  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, std::string src = "");
+	RTLIL::Cell* addReduceOr   (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, std::string src = "");
+	RTLIL::Cell* addReduceXor  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, std::string src = "");
+	RTLIL::Cell* addReduceXnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, std::string src = "");
+	RTLIL::Cell* addReduceBool (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, std::string src = "");
 
 	RTLIL::Cell* addShl    (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addShr    (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
@@ -998,7 +998,7 @@ public:
 	RTLIL::Cell* addMod (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addPow (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed = false, bool b_signed = false);
 
-	RTLIL::Cell* addLogicNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
+	RTLIL::Cell* addLogicNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, std::string src = "");
 	RTLIL::Cell* addLogicAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addLogicOr  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 
@@ -1057,21 +1057,21 @@ public:
 
 	// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.
 
-	RTLIL::SigSpec Not (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false);
-	RTLIL::SigSpec Pos (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false);
+	RTLIL::SigSpec Not (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, std::string src = "");
+	RTLIL::SigSpec Pos (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, std::string src = "");
 	RTLIL::SigSpec Bu0 (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false);
-	RTLIL::SigSpec Neg (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false);
+	RTLIL::SigSpec Neg (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, std::string src = "");
 
 	RTLIL::SigSpec And  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false);
 	RTLIL::SigSpec Or   (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false);
 	RTLIL::SigSpec Xor  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false);
 	RTLIL::SigSpec Xnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false);
 
-	RTLIL::SigSpec ReduceAnd  (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false);
-	RTLIL::SigSpec ReduceOr   (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false);
-	RTLIL::SigSpec ReduceXor  (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false);
-	RTLIL::SigSpec ReduceXnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false);
-	RTLIL::SigSpec ReduceBool (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false);
+	RTLIL::SigSpec ReduceAnd  (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, std::string src = "");
+	RTLIL::SigSpec ReduceOr   (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, std::string src = "");
+	RTLIL::SigSpec ReduceXor  (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, std::string src = "");
+	RTLIL::SigSpec ReduceXnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, std::string src = "");
+	RTLIL::SigSpec ReduceBool (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, std::string src = "");
 
 	RTLIL::SigSpec Shl    (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false);
 	RTLIL::SigSpec Shr    (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false);
@@ -1096,7 +1096,7 @@ public:
 	RTLIL::SigSpec Mod (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false);
 	RTLIL::SigSpec Pow (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool a_signed = false, bool b_signed = false);
 
-	RTLIL::SigSpec LogicNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false);
+	RTLIL::SigSpec LogicNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, std::string src = "");
 	RTLIL::SigSpec LogicAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false);
 	RTLIL::SigSpec LogicOr  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false);
 
diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index 9f6dd02d0..9593ef27a 100644
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -55,19 +55,19 @@ struct AlumaccWorker
 
 		RTLIL::SigSpec get_gt() {
 			if (GetSize(cached_gt) == 0)
-				cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()));
+				cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()), false, alu_cell->attributes["\\src"].decode_string());
 			return cached_gt;
 		}
 
 		RTLIL::SigSpec get_eq() {
 			if (GetSize(cached_eq) == 0)
-				cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort("\\X"));
+				cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort("\\X"), false, alu_cell->attributes["\\src"].decode_string());
 			return cached_eq;
 		}
 
 		RTLIL::SigSpec get_ne() {
 			if (GetSize(cached_ne) == 0)
-				cached_ne = alu_cell->module->Not(NEW_ID, get_eq());
+				cached_ne = alu_cell->module->Not(NEW_ID, get_eq(), false, alu_cell->attributes["\\src"].decode_string());
 			return cached_ne;
 		}
 
@@ -75,7 +75,7 @@ struct AlumaccWorker
 			if (GetSize(cached_cf) == 0) {
 				cached_cf = alu_cell->getPort("\\CO");
 				log_assert(GetSize(cached_cf) >= 1);
-				cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1]);
+				cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->attributes["\\src"].decode_string());
 			}
 			return cached_cf;
 		}
@@ -352,10 +352,14 @@ struct AlumaccWorker
 		{
 			auto n = it.second;
 			auto cell = module->addCell(NEW_ID, "$macc");
+			auto src = n->cell->attributes["\\src"].decode_string();
+
 			macc_counter++;
 
 			log("  creating $macc cell for %s: %s\n", log_id(n->cell), log_id(cell));
 
+			if (!src.empty()) cell->attributes["\\src"] = src;
+
 			n->macc.optimize(GetSize(n->y));
 			n->macc.to_cell(cell);
 			cell->setPort("\\Y", n->y);
@@ -452,6 +456,7 @@ struct AlumaccWorker
 
 	void replace_alu()
 	{
+		std::string src("");
 		for (auto &it1 : sig_alu)
 		for (auto n : it1.second)
 		{
@@ -475,6 +480,9 @@ struct AlumaccWorker
 				log("%s%s", i ? ", ": "", log_id(n->cells[i]));
 			log(": %s\n", log_id(n->alu_cell));
 
+			src = n->cells.size() > 0 ? n->cells[0]->attributes["\\src"].decode_string() : "";
+			if (!src.empty()) n->alu_cell->attributes["\\src"] = src;
+
 			n->alu_cell->setPort("\\A", n->a);
 			n->alu_cell->setPort("\\B", n->b);
 			n->alu_cell->setPort("\\CI", GetSize(n->c) ? n->c : RTLIL::S0);
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index c8104fb7e..71d708c18 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -478,11 +478,15 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare
 		auto cell_type = cell->type;
 		auto cell_name = cell->name;
 		auto cell_connections = cell->connections();
+		std::string src = cell->attributes["\\src"].decode_string();
+
 		module->remove(cell);
 
 		cell_mapping &cm = cell_mappings[cell_type];
 		RTLIL::Cell *new_cell = module->addCell(cell_name, prepare_mode ? cm.cell_name : "\\" + cm.cell_name);
 
+		if (!src.empty()) new_cell->attributes["\\src"] = src;
+
 		bool has_q = false, has_qn = false;
 		for (auto &port : cm.ports) {
 			if (port.second == 'Q') has_q = true;
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index ae89453d0..acc5d7471 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -172,6 +172,7 @@ struct TechmapWorker
 
 		std::string orig_cell_name;
 		pool<string> extra_src_attrs;
+		std::string src = cell->attributes["\\src"].decode_string();
 
 		if (!flatten_mode)
 		{
@@ -340,6 +341,8 @@ struct TechmapWorker
 			RTLIL::Cell *c = module->addCell(c_name, it.second);
 			design->select(module, c);
 
+			if (!src.empty()) c->attributes["\\src"] = src;
+
 			if (!flatten_mode && c->type.substr(0, 2) == "\\$")
 				c->type = c->type.substr(1);
 
@@ -464,7 +467,9 @@ struct TechmapWorker
 			log_assert(cell == module->cell(cell->name));
 			bool mapped_cell = false;
 
+			std::string src       = cell->attributes["\\src"].decode_string();
 			std::string cell_type = cell->type.str();
+
 			if (in_recursion && cell_type.substr(0, 2) == "\\$")
 				cell_type = cell_type.substr(1);
 
@@ -512,6 +517,8 @@ struct TechmapWorker
 								extmapper_module = extmapper_design->addModule(m_name);
 								RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
 
+								if (!src.empty()) extmapper_cell->attributes["\\src"] = src;
+
 								int port_counter = 1;
 								for (auto &c : extmapper_cell->connections_) {
 									RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));

From 271e8ba7cdc223ba8ee745ac1a5c837235398c54 Mon Sep 17 00:00:00 2001
From: Jason Lowdermilk <jlowder@chipscan.us>
Date: Wed, 30 Aug 2017 11:46:41 -0600
Subject: [PATCH 3/5] fix indent level

---
 kernel/rtlil.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index f132d299b..9a97faf45 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1620,7 +1620,7 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth
 }
 
 #define DEF_METHOD(_func, _y_size, _type) \
-		RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, std::string src) { \
+	RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, std::string src) { \
 		RTLIL::Cell *cell = addCell(name, _type);           \
 		cell->parameters["\\A_SIGNED"] = is_signed;         \
 		cell->parameters["\\A_WIDTH"] = sig_a.size();       \
@@ -1630,7 +1630,7 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth
 		if (!src.empty()) cell->attributes["\\src"] = src;  \
 		return cell;                                        \
 	} \
-		RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, std::string src) { \
+	RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, std::string src) { \
 		RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size);    \
 		add ## _func(name, sig_a, sig_y, is_signed, src);   \
 		return sig_y;                                       \

From 8dc6083de7c0328a8cd1d6e7b76dfd528b7baa3a Mon Sep 17 00:00:00 2001
From: Jason Lowdermilk <jlowder@chipscan.us>
Date: Thu, 31 Aug 2017 14:51:56 -0600
Subject: [PATCH 4/5] updated to use get_src_attribute() and
 set_src_attribute().

---
 passes/techmap/alumacc.cc   | 7 +++----
 passes/techmap/dfflibmap.cc | 4 ++--
 passes/techmap/techmap.cc   | 6 ++----
 3 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index 9593ef27a..920448915 100644
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -352,13 +352,12 @@ struct AlumaccWorker
 		{
 			auto n = it.second;
 			auto cell = module->addCell(NEW_ID, "$macc");
-			auto src = n->cell->attributes["\\src"].decode_string();
 
 			macc_counter++;
 
 			log("  creating $macc cell for %s: %s\n", log_id(n->cell), log_id(cell));
 
-			if (!src.empty()) cell->attributes["\\src"] = src;
+			cell->set_src_attribute(n->cell->get_src_attribute());
 
 			n->macc.optimize(GetSize(n->y));
 			n->macc.to_cell(cell);
@@ -480,8 +479,8 @@ struct AlumaccWorker
 				log("%s%s", i ? ", ": "", log_id(n->cells[i]));
 			log(": %s\n", log_id(n->alu_cell));
 
-			src = n->cells.size() > 0 ? n->cells[0]->attributes["\\src"].decode_string() : "";
-			if (!src.empty()) n->alu_cell->attributes["\\src"] = src;
+			if (n->cells.size() > 0)
+				n->alu_cell->set_src_attribute(n->cells[0]->get_src_attribute());
 
 			n->alu_cell->setPort("\\A", n->a);
 			n->alu_cell->setPort("\\B", n->b);
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 71d708c18..4cb1489a8 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -478,14 +478,14 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare
 		auto cell_type = cell->type;
 		auto cell_name = cell->name;
 		auto cell_connections = cell->connections();
-		std::string src = cell->attributes["\\src"].decode_string();
+		std::string src = cell->get_src_attribute();
 
 		module->remove(cell);
 
 		cell_mapping &cm = cell_mappings[cell_type];
 		RTLIL::Cell *new_cell = module->addCell(cell_name, prepare_mode ? cm.cell_name : "\\" + cm.cell_name);
 
-		if (!src.empty()) new_cell->attributes["\\src"] = src;
+		new_cell->set_src_attribute(src);
 
 		bool has_q = false, has_qn = false;
 		for (auto &port : cm.ports) {
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index acc5d7471..d9e81e808 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -172,7 +172,6 @@ struct TechmapWorker
 
 		std::string orig_cell_name;
 		pool<string> extra_src_attrs;
-		std::string src = cell->attributes["\\src"].decode_string();
 
 		if (!flatten_mode)
 		{
@@ -341,7 +340,7 @@ struct TechmapWorker
 			RTLIL::Cell *c = module->addCell(c_name, it.second);
 			design->select(module, c);
 
-			if (!src.empty()) c->attributes["\\src"] = src;
+			c->set_src_attribute(cell->get_src_attribute());
 
 			if (!flatten_mode && c->type.substr(0, 2) == "\\$")
 				c->type = c->type.substr(1);
@@ -467,7 +466,6 @@ struct TechmapWorker
 			log_assert(cell == module->cell(cell->name));
 			bool mapped_cell = false;
 
-			std::string src       = cell->attributes["\\src"].decode_string();
 			std::string cell_type = cell->type.str();
 
 			if (in_recursion && cell_type.substr(0, 2) == "\\$")
@@ -517,7 +515,7 @@ struct TechmapWorker
 								extmapper_module = extmapper_design->addModule(m_name);
 								RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
 
-								if (!src.empty()) extmapper_cell->attributes["\\src"] = src;
+								extmapper_cell->set_src_attribute(cell->get_src_attribute());
 
 								int port_counter = 1;
 								for (auto &c : extmapper_cell->connections_) {

From 8a66bd30c67c753149a195b951a3191d8e5e3304 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 1 Sep 2017 12:26:55 +0200
Subject: [PATCH 5/5] Update more stuff to use get_src_attribute() and
 set_src_attribute()

---
 kernel/rtlil.cc           | 2 +-
 passes/techmap/alumacc.cc | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index faddcd994..9539861cd 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1643,7 +1643,7 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth
 		cell->parameters["\\Y_WIDTH"] = sig_y.size();       \
 		cell->setPort("\\A", sig_a);                        \
 		cell->setPort("\\Y", sig_y);                        \
-		if (!src.empty()) cell->attributes["\\src"] = src;  \
+		cell->set_src_attribute(src);                       \
 		return cell;                                        \
 	} \
 	RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, std::string src) { \
diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index 920448915..95be7ab3b 100644
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -55,19 +55,19 @@ struct AlumaccWorker
 
 		RTLIL::SigSpec get_gt() {
 			if (GetSize(cached_gt) == 0)
-				cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()), false, alu_cell->attributes["\\src"].decode_string());
+				cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()), false, alu_cell->get_src_attribute());
 			return cached_gt;
 		}
 
 		RTLIL::SigSpec get_eq() {
 			if (GetSize(cached_eq) == 0)
-				cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort("\\X"), false, alu_cell->attributes["\\src"].decode_string());
+				cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort("\\X"), false, alu_cell->get_src_attribute());
 			return cached_eq;
 		}
 
 		RTLIL::SigSpec get_ne() {
 			if (GetSize(cached_ne) == 0)
-				cached_ne = alu_cell->module->Not(NEW_ID, get_eq(), false, alu_cell->attributes["\\src"].decode_string());
+				cached_ne = alu_cell->module->Not(NEW_ID, get_eq(), false, alu_cell->get_src_attribute());
 			return cached_ne;
 		}
 
@@ -75,7 +75,7 @@ struct AlumaccWorker
 			if (GetSize(cached_cf) == 0) {
 				cached_cf = alu_cell->getPort("\\CO");
 				log_assert(GetSize(cached_cf) >= 1);
-				cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->attributes["\\src"].decode_string());
+				cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->get_src_attribute());
 			}
 			return cached_cf;
 		}