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removing call to dump_attributes to remove possibility of generating invalid verilog 

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
This commit is contained in:
Ethan Mahintorabi 2024-01-30 00:56:07 +00:00
parent 33fe2e4613
commit 3076875fff
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backends/verilog/verilog_backend.cc
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@ -1058,7 +1058,6 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");
dump_attributes(f, "", cell->attributes, " ");
dump_cell_expr_port(f, cell, "A", false);
f << stringf(";\n");
return true;