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adffs test update (equiv_opt -multiclock)

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SergeyDegtyar 2019-09-17 11:53:49 +03:00 committed by Miodrag Milanovic
parent bb70eb977d
commit 305672170b
1 changed files with 6 additions and 5 deletions
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11
tests/xilinx/adffs.ys
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@ -1,13 +1,14 @@
read_verilog adffs.v read_verilog adffs.v
proc proc
async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
flatten flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check equiv_opt -multiclock -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG select -assert-count 1 t:BUFG
select -assert-count 3 t:FDRE select -assert-count 2 t:FDCE
select -assert-count 1 t:FDRE
select -assert-count 1 t:FDRE_1 select -assert-count 1 t:FDRE_1
select -assert-count 5 t:LUT2 select -assert-count 1 t:LUT1
select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 %% t:* %D select -assert-count 2 t:LUT2
select -assert-none t:BUFG t:FDCE t:FDRE t:FDRE_1 t:LUT1 t:LUT2 %% t:* %D