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Pack Y register

This commit is contained in:
Eddie Hung 2019-07-22 15:05:16 -07:00
parent 5e70b8a22b
commit 304cefbbe2
2 changed files with 38 additions and 22 deletions
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38
passes/pmgen/ice40_dsp.cc
View File

@ -80,20 +80,25 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
SigSpec B = st.sigB; SigSpec B = st.sigB;
B.extend_u0(16, b_signed); B.extend_u0(16, b_signed);
// MAC only if ffS exists and adder's other input (sigS)
// is output of ffS
bool accum = (st.ffS && st.sigS == st.ffS->getPort("\\Q"));
SigSpec CD; SigSpec CD;
if (st.ffS) { bool CD_signed = false;
if (st.muxAB != st.addAB) {
if (st.muxA) if (st.muxA)
CD = st.muxA->getPort("\\B"); CD = st.muxA->getPort("\\B");
else if (st.muxB) else if (st.muxB)
CD = st.muxB->getPort("\\A"); CD = st.muxB->getPort("\\A");
else log_abort();
CD_signed = a_signed && b_signed; // TODO: Do muxes have [AB]_SIGNED?
} }
else if (!accum) else if (st.addAB) {
CD = st.sigS.extend_u0(32, st.sigS_signed); if (st.addA)
CD.extend_u0(32, a_signed && b_signed); CD = st.addAB->getPort("\\B");
else if (st.addB)
CD = st.addAB->getPort("\\A");
else log_abort();
CD_signed = st.sigS_signed;
}
CD.extend_u0(32, CD_signed);
cell->setPort("\\A", A); cell->setPort("\\A", A);
cell->setPort("\\B", B); cell->setPort("\\B", B);
@ -153,15 +158,21 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
// SB_MAC16 Output Interface // SB_MAC16 Output Interface
if (st.addAB) log_cell(st.addAB);
SigSpec O = st.ffS ? st.sigS : (st.addAB ? st.addAB->getPort("\\Y") : st.sigY); SigSpec O = st.ffS ? st.sigS : (st.addAB ? st.addAB->getPort("\\Y") : st.sigY);
if (GetSize(O) < 32) if (GetSize(O) < 32)
O.append(pm.module->addWire(NEW_ID, 32-GetSize(O))); O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
cell->setPort("\\O", O); cell->setPort("\\O", O);
// MAC only if ffS exists and adder's other input (sigS)
// is output of ffS
bool accum = false;
if (st.addAB) { if (st.addAB) {
log_warning("sigS = %s\n", log_signal(st.sigS)); if (st.addA)
accum = (st.ffS && st.addAB->getPort("\\B") == st.ffS->getPort("\\Q"));
else if (st.addB)
accum = (st.ffS && st.addAB->getPort("\\A") == st.ffS->getPort("\\Q"));
else log_abort();
if (accum) if (accum)
log(" accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type)); log(" accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
else else
@ -200,12 +211,12 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffS ? 1 : (st.addAB ? 0 : 3), 2)); cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffS ? 1 : (st.addAB ? 0 : 3), 2));
cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2)); cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2));
cell->setParam("\\TOPADDSUB_UPPERINPUT", st.ffS ? State::S0 : State::S1); cell->setParam("\\TOPADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
cell->setParam("\\TOPADDSUB_CARRYSELECT", Const(3, 2)); cell->setParam("\\TOPADDSUB_CARRYSELECT", Const(3, 2));
cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffS ? 1 : (st.addAB ? 0 : 3), 2)); cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffS ? 1 : (st.addAB ? 0 : 3), 2));
cell->setParam("\\BOTADDSUB_LOWERINPUT", Const(2, 2)); cell->setParam("\\BOTADDSUB_LOWERINPUT", Const(2, 2));
cell->setParam("\\BOTADDSUB_UPPERINPUT", st.ffS ? State::S0 : State::S1); cell->setParam("\\BOTADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2)); cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2));
cell->setParam("\\MODE_8x8", State::S0); cell->setParam("\\MODE_8x8", State::S0);
@ -215,7 +226,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
pm.autoremove(st.mul); pm.autoremove(st.mul);
pm.autoremove(st.ffY); pm.autoremove(st.ffY);
pm.autoremove(st.addAB); pm.autoremove(st.addAB);
pm.autoremove(st.ffS); if (st.ffS)
st.ffS->connections_.at("\\Q").replace(st.sigS, pm.module->addWire(NEW_ID, GetSize(st.sigS)));
} }
struct Ice40DspPass : public Pass { struct Ice40DspPass : public Pass {

12
passes/pmgen/ice40_dsp.pmg
View File

@ -143,17 +143,21 @@ endcode
match ffS match ffS
if muxAB if muxAB
select ffS->type.in($dff) select ffS->type.in($dff)
select nusers(port(ffS, \D)) == 2 filter nusers(port(muxAB, \Y)) == 2
index <SigSpec> port(ffS, \D) === port(muxAB, \Y) filter includes(port(ffS, \D).to_sigbit_set(), port(muxAB, \Y).to_sigbit_set())
index <SigSpec> port(ffS, \Q) === sigS
optional optional
endmatch endmatch
code clock clock_pol code clock clock_pol sigS
if (ffS) { if (ffS) {
SigBit c = port(ffS, \CLK).as_bit(); SigBit c = port(ffS, \CLK).as_bit();
bool cp = param(ffS, \CLK_POLARITY).as_bool(); bool cp = param(ffS, \CLK_POLARITY).as_bool();
if (port(ffS, \Q) != sigS) {
sigS = port(muxAB, \Y);
sigS.replace(port(ffS, \D), port(ffS, \Q));
}
if (clock != SigBit() && (c != clock || cp != clock_pol)) if (clock != SigBit() && (c != clock || cp != clock_pol))
reject; reject;