riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

stop check_signal_in_fanout from traversing FFs

This commit is contained in:
tklam 2018-10-13 23:11:19 +08:00
parent 3c5406c31b
commit 302edf0429
1 changed files with 12 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
passes/equiv/equiv_make.cc
View File

@ -42,6 +42,14 @@ struct EquivMakeWorker
dict<SigBit, pool<Cell*>> bit2driven; // map: bit <--> and its driven cells
CellTypes comb_ct;
EquivMakeWorker()
{
comb_ct.setup_internals();
comb_ct.setup_stdcells();
}
void read_blacklists()
{
for (auto fn : blacklists)
@ -415,9 +423,12 @@ struct EquivMakeWorker
auto driven_cells = bit2driven.at(source_bit);
for (auto driven_cell: driven_cells)
{
if (visited_cells.count(driven_cell) > 0)
bool is_comb = comb_ct.cell_known(cell->type);
if (is_comb)
continue;
if (visited_cells.count(driven_cell) > 0)
continue;
visited_cells.insert(driven_cell);
for (auto &conn: driven_cell->connections())