riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Bugfix in ice40_dsp 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-02-21 13:28:46 +01:00
parent 84999a7e68
commit 2fe1c830eb
3 changed files with 35 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
passes/pmgen/ice40_dsp.cc
View File

@ -91,8 +91,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
cell->setPort("\\C", CD.extract(0, 16)); cell->setPort("\\C", CD.extract(0, 16));
cell->setPort("\\D", CD.extract(16, 16)); cell->setPort("\\D", CD.extract(16, 16));
cell->setParam("\\A_REG", pm.st.ffA ? State::S0 : State::S1); cell->setParam("\\A_REG", pm.st.ffA ? State::S1 : State::S0);
cell->setParam("\\B_REG", pm.st.ffB ? State::S0 : State::S1); cell->setParam("\\B_REG", pm.st.ffB ? State::S1 : State::S0);
cell->setPort("\\AHOLD", State::S0); cell->setPort("\\AHOLD", State::S0);
cell->setPort("\\BHOLD", State::S0); cell->setPort("\\BHOLD", State::S0);

1
techlibs/ice40/tests/.gitignore vendored
View File

@ -5,6 +5,7 @@
/test_dsp_model_ref.v /test_dsp_model_ref.v
/test_dsp_model_uut.v /test_dsp_model_uut.v
/test_dsp_map /test_dsp_map
/test_dsp_map.vcd
/test_dsp_map_tb.v /test_dsp_map_tb.v
/test_dsp_map_top.v /test_dsp_map_top.v
/test_dsp_map_syn.v /test_dsp_map_syn.v

14
techlibs/ice40/tests/test_dsp_map.sh
View File

@ -1,6 +1,8 @@
#!/bin/bash #!/bin/bash
set -ex set -ex
for iter in {1..100}
do
SZA=$(( 3 + $RANDOM % 13 )) SZA=$(( 3 + $RANDOM % 13 ))
SZB=$(( 3 + $RANDOM % 13 )) SZB=$(( 3 + $RANDOM % 13 ))
SZO=$(( 3 + $RANDOM % 29 )) SZO=$(( 3 + $RANDOM % 29 ))
@ -51,10 +53,14 @@ module testbench;
syn syn_inst (.clk0(clk0), .clk1(clk1), .reset(reset), .A(A), .B(B), .O(O_syn)); syn syn_inst (.clk0(clk0), .clk1(clk1), .reset(reset), .A(A), .B(B), .O(O_syn));
initial begin initial begin
// \$dumpfile("test_dsp_map.vcd");
// \$dumpvars(0, testbench);
#2; #2;
clk0 = 0; clk0 = 0;
clk1 = 0; clk1 = 0;
reset = 1; reset = 1;
reset = $RC;
A = 0; A = 0;
B = 0; B = 0;
@ -82,9 +88,10 @@ module testbench;
\$display("ERROR: O_top=%b O_syn=%b", O_top, O_syn); \$display("ERROR: O_top=%b O_syn=%b", O_top, O_syn);
\$stop; \$stop;
end end
\$display("OK O_top=O_syn=%b", O_top); // \$display("OK O_top=O_syn=%b", O_top);
end end
\$display("Test passed.");
\$finish; \$finish;
end end
endmodule endmodule
@ -93,3 +100,8 @@ EOT
../../../yosys -p 'read_verilog test_dsp_map_top.v; synth_ice40 -dsp; rename top syn; write_verilog test_dsp_map_syn.v' ../../../yosys -p 'read_verilog test_dsp_map_top.v; synth_ice40 -dsp; rename top syn; write_verilog test_dsp_map_syn.v'
iverilog -o test_dsp_map -s testbench test_dsp_map_tb.v test_dsp_map_top.v test_dsp_map_syn.v ../cells_sim.v iverilog -o test_dsp_map -s testbench test_dsp_map_tb.v test_dsp_map_top.v test_dsp_map_syn.v ../cells_sim.v
vvp -N test_dsp_map vvp -N test_dsp_map
done
: ""
: "#### All tests passed. ####"
: ""