riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed data/address width parameters

This commit is contained in:
Richard Herveille 2024-03-06 02:45:07 +01:00
parent b16cdaab35
commit 2fde482629
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
techlibs/intel/common/brams_map_m9k.v
View File

@ -63,10 +63,10 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
.width_byteena_a (1), // Forced value .width_byteena_a (1), // Forced value
.numwords_b ( NUMWORDS ), .numwords_b ( NUMWORDS ),
.numwords_a ( NUMWORDS ), .numwords_a ( NUMWORDS ),
.widthad_b ( CFG_DBITS ), .widthad_b ( CFG_ABITS ),
.width_b ( CFG_ABITS ), .width_b ( CFG_DBITS ),
.widthad_a ( CFG_DBITS ), .widthad_a ( CFG_ABITS ),
.width_a ( CFG_ABITS ) .width_a ( CFG_DBITS )
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.data_a(B1DATA), .data_a(B1DATA),
.address_a(B1ADDR), .address_a(B1ADDR),