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Added "splice -wires"

This commit is contained in:
Clifford Wolf 2015-04-13 19:28:12 +02:00
parent e305d85807
commit 2fc2f8f5b3
1 changed files with 20 additions and 9 deletions
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29
passes/cmds/splice.cc
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@ -36,6 +36,8 @@ struct SpliceWorker
bool sel_by_wire; bool sel_by_wire;
bool sel_any_bit; bool sel_any_bit;
bool no_outputs; bool no_outputs;
bool do_wires;
std::set<RTLIL::IdString> ports; std::set<RTLIL::IdString> ports;
std::set<RTLIL::IdString> no_ports; std::set<RTLIL::IdString> no_ports;
@ -209,23 +211,23 @@ struct SpliceWorker
std::vector<std::pair<RTLIL::Wire*, RTLIL::SigSpec>> rework_wires; std::vector<std::pair<RTLIL::Wire*, RTLIL::SigSpec>> rework_wires;
std::vector<Wire*> mod_wires = module->wires(); std::vector<Wire*> mod_wires = module->wires();
for (auto mod : mod_wires) for (auto wire : mod_wires)
if (!no_outputs && mod->port_output) { if ((!no_outputs && wire->port_output) || (do_wires && wire->name[0] == '\\')) {
if (!design->selected(module, mod)) if (!design->selected(module, wire))
continue; continue;
RTLIL::SigSpec sig = sigmap(mod); RTLIL::SigSpec sig = sigmap(wire);
if (driven_chunks.count(sig) > 0) if (driven_chunks.count(sig) > 0)
continue; continue;
RTLIL::SigSpec new_sig = get_spliced_signal(sig); RTLIL::SigSpec new_sig = get_spliced_signal(sig);
if (new_sig != sig) if (new_sig != sig)
rework_wires.push_back(std::pair<RTLIL::Wire*, RTLIL::SigSpec>(mod, new_sig)); rework_wires.push_back(std::pair<RTLIL::Wire*, RTLIL::SigSpec>(wire, new_sig));
} else } else
if (!mod->port_input) { if (!wire->port_input) {
RTLIL::SigSpec sig = sigmap(mod); RTLIL::SigSpec sig = sigmap(wire);
if (spliced_signals_cache.count(sig) && spliced_signals_cache.at(sig) != sig) if (spliced_signals_cache.count(sig) && spliced_signals_cache.at(sig) != sig)
rework_wires.push_back(std::pair<RTLIL::Wire*, RTLIL::SigSpec>(mod, spliced_signals_cache.at(sig))); rework_wires.push_back(std::pair<RTLIL::Wire*, RTLIL::SigSpec>(wire, spliced_signals_cache.at(sig)));
else if (sliced_signals_cache.count(sig) && sliced_signals_cache.at(sig) != sig) else if (sliced_signals_cache.count(sig) && sliced_signals_cache.at(sig) != sig)
rework_wires.push_back(std::pair<RTLIL::Wire*, RTLIL::SigSpec>(mod, sliced_signals_cache.at(sig))); rework_wires.push_back(std::pair<RTLIL::Wire*, RTLIL::SigSpec>(wire, sliced_signals_cache.at(sig)));
} }
for (auto &it : rework_wires) for (auto &it : rework_wires)
@ -268,6 +270,9 @@ struct SplicePass : public Pass {
log(" it is sufficient if the driver of any bit of a cell port is selected.\n"); log(" it is sufficient if the driver of any bit of a cell port is selected.\n");
log(" by default all bits must be selected.\n"); log(" by default all bits must be selected.\n");
log("\n"); log("\n");
log(" -wires\n");
log(" also add $slice and $concat cells to drive otherwise unused wires.\n");
log("\n");
log(" -no_outputs\n"); log(" -no_outputs\n");
log(" do not rewire selected module outputs.\n"); log(" do not rewire selected module outputs.\n");
log("\n"); log("\n");
@ -289,6 +294,7 @@ struct SplicePass : public Pass {
bool sel_by_wire = false; bool sel_by_wire = false;
bool sel_any_bit = false; bool sel_any_bit = false;
bool no_outputs = false; bool no_outputs = false;
bool do_wires = false;
std::set<RTLIL::IdString> ports, no_ports; std::set<RTLIL::IdString> ports, no_ports;
size_t argidx; size_t argidx;
@ -305,6 +311,10 @@ struct SplicePass : public Pass {
sel_any_bit = true; sel_any_bit = true;
continue; continue;
} }
if (args[argidx] == "-wires") {
do_wires = true;
continue;
}
if (args[argidx] == "-no_outputs") { if (args[argidx] == "-no_outputs") {
no_outputs = true; no_outputs = true;
continue; continue;
@ -348,6 +358,7 @@ struct SplicePass : public Pass {
worker.sel_by_wire = sel_by_wire; worker.sel_by_wire = sel_by_wire;
worker.sel_any_bit = sel_any_bit; worker.sel_any_bit = sel_any_bit;
worker.no_outputs = no_outputs; worker.no_outputs = no_outputs;
worker.do_wires = do_wires;
worker.ports = ports; worker.ports = ports;
worker.no_ports = no_ports; worker.no_ports = no_ports;
worker.run(); worker.run();