Merge remote-tracking branch 'origin/master' into xaig_arrival

passes/cmds/select.cc

@@ -664,7 +664,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
 		} else
 		if (arg == "%D") {
 			if (work_stack.size() < 2)
-				log_cmd_error("Must have at least two elements on the stack for operator %%d.\n");
+				log_cmd_error("Must have at least two elements on the stack for operator %%D.\n");
 			select_op_diff(design, work_stack[work_stack.size()-1], work_stack[work_stack.size()-2]);
 			work_stack[work_stack.size()-2] = work_stack[work_stack.size()-1];
 			work_stack.pop_back();
@@ -693,7 +693,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
 		} else
 		if (arg == "%C") {
 			if (work_stack.size() < 1)
-				log_cmd_error("Must have at least one element on the stack for operator %%M.\n");
+				log_cmd_error("Must have at least one element on the stack for operator %%C.\n");
 			select_op_module_to_cells(design, work_stack[work_stack.size()-1]);
 		} else
 		if (arg == "%c") {

passes/pmgen/Makefile.inc

@@ -4,7 +4,7 @@
 # --------------------------------------
 
 OBJS += passes/pmgen/test_pmgen.o
-passes/pmgen/test_pmgen.o: passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/peepopt_pm.h
+passes/pmgen/test_pmgen.o: passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/peepopt_pm.h passes/pmgen/xilinx_srl_pm.h
 $(eval $(call add_extra_objs,passes/pmgen/test_pmgen_pm.h))
 
 # --------------------------------------

passes/pmgen/ice40_dsp.cc

@@ -64,11 +64,6 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	bool mul_signed = st.mul->getParam("\\A_SIGNED").as_bool();
 
-	if (mul_signed) {
-		log("  inference of signed iCE40 DSP arithmetic is currently not supported.\n");
-		return;
-	}
-
 	log("  replacing $mul with SB_MAC16 cell.\n");
 
 	Cell *cell = pm.module->addCell(NEW_ID, "\\SB_MAC16");

techlibs/ecp5/cells_sim.v

@@ -226,14 +226,15 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
 	parameter REGSET = "RESET";
 	parameter [127:0] LSRMODE = "LSR";
 
-	reg muxce;
+	wire muxce;
-	always @(*)
+	generate
 		case (CEMUX)
-			"1": muxce = 1'b1;
+			"1": assign muxce = 1'b1;
-			"0": muxce = 1'b0;
+			"0": assign muxce = 1'b0;
-			"INV": muxce = ~CE;
+			"INV": assign muxce = ~CE;
-			default: muxce = CE;
+			default: assign muxce = CE;
 		endcase
+	endgenerate
 
 	wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
 	wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;

techlibs/ecp5/ecp5_gsr.cc

@@ -124,7 +124,7 @@ struct Ecp5GsrPass : public Pass {
 				SigBit lsr = sigmap(sig_lsr[0]);
 				if (!inverted_gsr.count(lsr))
 					continue;
-				cell->setParam(ID(SRMODE), Const("SYNC"));
+				cell->setParam(ID(SRMODE), Const("LSR_OVER_CE"));
 				cell->unsetPort(ID(LSR));
 			}
 

tests/ice40/macc.v

@@ -2,8 +2,8 @@
 Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 77].
 */
 module top(clk,a,b,c,set);
-parameter A_WIDTH = 4;
+parameter A_WIDTH = 6 /*4*/;
-parameter B_WIDTH = 3;
+parameter B_WIDTH = 6 /*3*/;
 input set;
 input clk;
 input signed [(A_WIDTH - 1):0] a;

tests/ice40/macc.ys

@@ -1,10 +1,13 @@
 read_verilog macc.v
 proc
 hierarchy -top top
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
+#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
+
+equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 -dsp
+async2sync
+equiv_opt -run prove: -assert null
+
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 38 t:SB_LUT4
+select -assert-count 1 t:SB_MAC16
-select -assert-count 3 t:SB_CARRY
+select -assert-none t:SB_MAC16 %% t:* %D
-select -assert-count 7 t:SB_DFFSR
-select -assert-none t:SB_LUT4 t:SB_CARRY t:SB_DFFSR %% t:* %D