mirror of https://github.com/YosysHQ/yosys.git
set "keep" on modules with $assert cells in "hierarchy"
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@ -286,6 +286,17 @@ void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib, bool f
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log("Removed %zd unused modules.\n", del_modules.size());
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log("Removed %zd unused modules.\n", del_modules.size());
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}
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}
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bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
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{
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if (cache.count(mod) == 0)
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for (auto c : mod->cells()) {
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RTLIL::Module *m = mod->design->module(c->type);
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if ((m != nullptr && set_keep_assert(cache, m)) || c->type == "$assert")
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return cache[mod] = true;
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}
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return cache[mod];
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}
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struct HierarchyPass : public Pass {
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struct HierarchyPass : public Pass {
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HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { }
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HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { }
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virtual void help()
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virtual void help()
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@ -317,6 +328,11 @@ struct HierarchyPass : public Pass {
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log(" per default this pass also converts positional arguments in cells\n");
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log(" per default this pass also converts positional arguments in cells\n");
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log(" to arguments using port names. this option disables this behavior.\n");
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log(" to arguments using port names. this option disables this behavior.\n");
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log("\n");
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log("\n");
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log(" -nokeep_asserts\n");
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log(" per default this pass sets the \"keep\" attribute on all modules\n");
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log(" that directly or indirectly contain one or more $assert cells. this\n");
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log(" option disables this behavior.\n");
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log("\n");
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log(" -top <module>\n");
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log(" -top <module>\n");
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log(" use the specified top module to built a design hierarchy. modules\n");
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log(" use the specified top module to built a design hierarchy. modules\n");
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log(" outside this tree (unused modules) are removed.\n");
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log(" outside this tree (unused modules) are removed.\n");
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@ -353,6 +369,7 @@ struct HierarchyPass : public Pass {
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bool generate_mode = false;
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bool generate_mode = false;
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bool keep_positionals = false;
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bool keep_positionals = false;
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bool nokeep_asserts = false;
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std::vector<std::string> generate_cells;
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std::vector<std::string> generate_cells;
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std::vector<generate_port_decl_t> generate_ports;
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std::vector<generate_port_decl_t> generate_ports;
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@ -410,6 +427,10 @@ struct HierarchyPass : public Pass {
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keep_positionals = true;
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keep_positionals = true;
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continue;
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continue;
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}
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}
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if (args[argidx] == "-nokeep_asserts") {
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nokeep_asserts = true;
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continue;
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}
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if (args[argidx] == "-libdir" && argidx+1 < args.size()) {
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if (args[argidx] == "-libdir" && argidx+1 < args.size()) {
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libdirs.push_back(args[++argidx]);
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libdirs.push_back(args[++argidx]);
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continue;
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continue;
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@ -477,6 +498,15 @@ struct HierarchyPass : public Pass {
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mod_it.second->attributes.erase("\\top");
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mod_it.second->attributes.erase("\\top");
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}
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}
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if (!nokeep_asserts) {
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std::map<RTLIL::Module*, bool> cache;
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for (auto mod : design->modules())
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if (set_keep_assert(cache, mod)) {
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log("Module %s directly or indirectly contains $assert cells -> setting \"keep\" attribute.\n", log_id(mod));
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mod->set_bool_attribute("\\keep");
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}
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}
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if (!keep_positionals)
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if (!keep_positionals)
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{
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{
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std::set<RTLIL::Module*> pos_mods;
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std::set<RTLIL::Module*> pos_mods;
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