mirror of https://github.com/YosysHQ/yosys.git
Fix $__XILINX_MUXF78 box timing
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09ac274716
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@ -17,7 +17,7 @@ MUXF8 2 1 3 1
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# Inputs: I0 I1 I2 I3 S0 S1
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# Outputs: O
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$__MUXF78 3 1 6 1
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190 193 217 223 296 273
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294 297 311 317 390 273
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# CARRY4 + CARRY4_[ABCD]X
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# Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
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