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Do not simplemap for variable test

This commit is contained in:
Eddie Hung 2019-08-28 09:26:08 -07:00
parent 975aaf190f
commit 2e9e745efa
1 changed files with 2 additions and 2 deletions
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4
tests/xilinx/xilinx_srl.ys
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@ -40,14 +40,14 @@ hierarchy -top xilinx_srl_variable_test
prep prep
design -save gold design -save gold
simplemap t:$dff t:$dffe
xilinx_srl -variable xilinx_srl -variable
opt opt
#stat #stat
# show -width # show -width
# write_verilog -noexpr -norename # write_verilog -noexpr -norename
select -assert-count 1 t:$_DFF_P_ select -assert-count 1 t:$dff
select -assert-count 1 t:$dff r:WIDTH=1 %i
select -assert-count 2 t:$__XILINX_SHREG_ select -assert-count 2 t:$__XILINX_SHREG_
design -stash gate design -stash gate