riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Also allow "module foobar(input foo, output bar, ...);" syntax

This commit is contained in:
Clifford Wolf 2014-08-07 16:41:27 +02:00
parent 312ee00c9e
commit 2dc3333734
1 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
frontends/verilog/parser.y
View File

@ -247,8 +247,7 @@ single_module_para:
};
module_args_opt:
'(' ')' | /* empty */ | '(' module_args optional_comma ')' |
'(' '.' '.' '.' ')' { do_not_require_port_stubs = true; };
'(' ')' | /* empty */ | '(' module_args optional_comma ')';
module_args:
module_arg | module_args ',' module_arg;
@ -297,7 +296,10 @@ module_arg:
ast_stack.back()->children.push_back(node);
append_attr(node, $1);
delete $4;
} module_arg_opt_assignment;
} module_arg_opt_assignment |
'.' '.' '.' {
do_not_require_port_stubs = true;
};
wire_type:
{