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update type and variable names 

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
This commit is contained in:
Ethan Mahintorabi 2024-02-15 23:59:19 +00:00
parent 8566489d85
commit 2d8343d423
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GPG Key ID: 824E41B920BEA252
1 changed files with 7 additions and 7 deletions
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14
passes/cmds/stat.cc
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@ -28,9 +28,9 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
struct cell_data_t { struct cell_area_t {
double area; double area;
bool is_flip_flop; bool is_sequential;
}; };
struct statdata_t struct statdata_t
@ -80,7 +80,7 @@ struct statdata_t
#undef X #undef X
} }
statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict<IdString, cell_data_t> &cell_properties, string techname) statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict<IdString, cell_area_t> &cell_properties, string techname)
{ {
tech = techname; tech = techname;
@ -139,8 +139,8 @@ struct statdata_t
if (!cell_properties.empty()) { if (!cell_properties.empty()) {
if (cell_properties.count(cell_type)) { if (cell_properties.count(cell_type)) {
cell_data_t cell_data = cell_properties.at(cell_type); cell_area_t cell_data = cell_properties.at(cell_type);
if (cell_data.is_flip_flop) { if (cell_data.is_sequential) {
sequential_area += cell_data.area; sequential_area += cell_data.area;
} }
area += cell_data.area; area += cell_data.area;
@ -338,7 +338,7 @@ statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTL
return mod_data; return mod_data;
} }
void read_liberty_cellarea(dict<IdString, cell_data_t> &cell_properties, string liberty_file) void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_properties, string liberty_file)
{ {
std::ifstream f; std::ifstream f;
f.open(liberty_file.c_str()); f.open(liberty_file.c_str());
@ -397,7 +397,7 @@ struct StatPass : public Pass {
bool width_mode = false, json_mode = false; bool width_mode = false, json_mode = false;
RTLIL::Module *top_mod = nullptr; RTLIL::Module *top_mod = nullptr;
std::map<RTLIL::IdString, statdata_t> mod_stat; std::map<RTLIL::IdString, statdata_t> mod_stat;
dict<IdString, cell_data_t> cell_properties; dict<IdString, cell_area_t> cell_properties;
string techname; string techname;
size_t argidx; size_t argidx;