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Add signed opt_expr tests

This commit is contained in:
Eddie Hung 2019-08-06 15:40:30 -07:00
parent 769c750c22
commit 2d1b517b01
1 changed files with 50 additions and 0 deletions
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50
tests/various/opt_expr.ys
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@ -24,6 +24,31 @@ sat -verify -prove-asserts -show-ports miter
########## ##########
read_verilog <<EOT
module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
assign o = (i << 4) + j;
endmodule
EOT
hierarchy -auto-top
proc
design -save gold
opt_expr -fine
wreduce
select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
##########
read_verilog <<EOT read_verilog <<EOT
module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o); module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
assign o = j - (i << 4); assign o = j - (i << 4);
@ -49,6 +74,31 @@ sat -verify -prove-asserts -show-ports miter
########## ##########
read_verilog <<EOT
module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
assign o = j - (i << 4);
endmodule
EOT
hierarchy -auto-top
proc
design -save gold
opt_expr -fine
wreduce
select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
##########
read_verilog <<EOT read_verilog <<EOT
module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o); module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
assign o = (i << 4) - j; assign o = (i << 4) - j;