mirror of https://github.com/YosysHQ/yosys.git
replace space indent with tab indent
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acddc36389
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@ -221,8 +221,6 @@ code
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{
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subpattern(tail);
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}
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} else {
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if (GetSize(chain) > GetSize(longest_chain))
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longest_chain = chain;
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@ -259,7 +259,6 @@ generate
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assign PORT_R_RD_DATA[19:0] = B_read_data[19:0];
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assign PORT_R_RD_DATA[39:20] = A_read_data[19:0];
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end
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endgenerate
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// port width
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@ -314,9 +313,7 @@ RAM1K20 #(
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// Disable ECC for SDP
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.ECC_EN(1'b0),
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.ECC_BYPASS(1'b1),
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.BUSY_FB(1'b0)
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);
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@ -644,7 +644,6 @@ module RAM1K18 (
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input B_DOUT_CLK,
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input B_DOUT_EN,
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input B_DOUT_SRST_N,
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input A_EN,
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input B_EN,
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input SII_LOCK,
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