mirror of https://github.com/YosysHQ/yosys.git
Correction and optimization of nowrshmsk
This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that nowrshmsk is actually tested. Stride is extracted from indexing of two-dimensional packed arrays and variable slices on the form dst[i*stride +: width] = src, and is used to optimize the generated CASE block. Also uses less confusing variable names for indexing of lhs wires.
This commit is contained in:
Dag Lem
parent
1ddb0892c1
commit
2cab4ff173
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@ -35,12 +35,25 @@
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#include <stdarg.h>
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#include <stdlib.h>
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#include <math.h>
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// For std::gcd in C++17
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// #include <numeric>
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YOSYS_NAMESPACE_BEGIN
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using namespace AST;
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using namespace AST_INTERNAL;
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// gcd computed by Euclidian division.
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// To be replaced by C++17 std::gcd
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template<class I> I gcd(I a, I b) {
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while (b != 0) {
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I tmp = b;
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b = a%b;
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a = tmp;
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}
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return std::abs(a);
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}
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void AstNode::set_in_lvalue_flag(bool flag, bool no_descend)
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{
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if (flag != in_lvalue_from_above) {
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@ -2818,27 +2831,12 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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if (!children[0]->id2ast->range_valid)
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goto skip_dynamic_range_lvalue_expansion;
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int source_width = children[0]->id2ast->range_left - children[0]->id2ast->range_right + 1;
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int source_offset = children[0]->id2ast->range_right;
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int result_width = 1;
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int stride = 1;
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AST::AstNode *member_node = get_struct_member(children[0]);
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if (member_node) {
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// Clamp chunk to range of member within struct/union.
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log_assert(!source_offset && !children[0]->id2ast->range_swapped);
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source_width = member_node->range_left - member_node->range_right + 1;
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// When the (* nowrshmsk *) attribute is set, a CASE block is generated below
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// to select the indexed bit slice. When a multirange array is indexed, the
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// start of each possible slice is separated by the bit stride of the last
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// index dimension, and we can optimize the CASE block accordingly.
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// The dimension of the original array expression is saved in the 'integer' field.
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int dims = children[0]->integer;
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stride = source_width;
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for (int dim = 0; dim < dims; dim++) {
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stride /= get_struct_range_width(member_node, dim);
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}
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}
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int wire_width = member_node ?
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member_node->range_left - member_node->range_right + 1 :
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children[0]->id2ast->range_left - children[0]->id2ast->range_right + 1;
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int wire_offset = children[0]->id2ast->range_right;
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int result_width = 1;
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AstNode *shift_expr = NULL;
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AstNode *range = children[0]->children[0];
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@ -2851,30 +2849,102 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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else
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shift_expr = range->children[0]->clone();
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bool use_case_method = false;
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if (children[0]->id2ast->attributes.count(ID::nowrshmsk)) {
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AstNode *node = children[0]->id2ast->attributes.at(ID::nowrshmsk);
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while (node->simplify(true, stage, -1, false)) { }
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if (node->type != AST_CONSTANT)
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input_error("Non-constant value for `nowrshmsk' attribute on `%s'!\n", children[0]->id2ast->str.c_str());
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if (node->asAttrConst().as_bool())
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use_case_method = true;
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}
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bool use_case_method = children[0]->id2ast->get_bool_attribute(ID::nowrshmsk);
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if (!use_case_method && current_always->detect_latch(children[0]->str))
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use_case_method = true;
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if (use_case_method)
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{
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if (use_case_method) {
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// big case block
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int stride = 1;
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long long bitno_div = stride;
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int case_width_hint;
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bool case_sign_hint;
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shift_expr->detectSignWidth(case_width_hint, case_sign_hint);
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int max_width = case_width_hint;
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if (member_node) { // Member in packed struct/union
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// Clamp chunk to range of member within struct/union.
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log_assert(!wire_offset && !children[0]->id2ast->range_swapped);
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// When the (* nowrshmsk *) attribute is set, a CASE block is generated below
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// to select the indexed bit slice. When a multirange array is indexed, the
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// start of each possible slice is separated by the bit stride of the last
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// index dimension, and we can optimize the CASE block accordingly.
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// The dimension of the original array expression is saved in the 'integer' field.
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int dims = children[0]->integer;
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stride = wire_width;
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for (int dim = 0; dim < dims; dim++) {
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stride /= get_struct_range_width(member_node, dim);
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}
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bitno_div = stride;
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} else {
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// Extract (index)*(width) from non_opt_range pattern ((@selfsz@((index)*(width)))+(0)).
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AstNode *lsb_expr =
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shift_expr->type == AST_ADD && shift_expr->children[0]->type == AST_SELFSZ &&
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shift_expr->children[1]->type == AST_CONSTANT && shift_expr->children[1]->integer == 0 ?
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shift_expr->children[0]->children[0] :
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shift_expr;
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// Extract stride from indexing of two-dimensional packed arrays and
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// variable slices on the form dst[i*stride +: width] = src.
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if (lsb_expr->type == AST_MUL &&
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(lsb_expr->children[0]->type == AST_CONSTANT ||
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lsb_expr->children[1]->type == AST_CONSTANT))
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{
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int stride_ix = lsb_expr->children[1]->type == AST_CONSTANT;
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stride = (int)lsb_expr->children[stride_ix]->integer;
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bitno_div = stride != 0 ? stride : 1;
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// Check whether i*stride can overflow.
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int i_width;
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bool i_sign;
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lsb_expr->children[1 - stride_ix]->detectSignWidth(i_width, i_sign);
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int stride_width;
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bool stride_sign;
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lsb_expr->children[stride_ix]->detectSignWidth(stride_width, stride_sign);
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max_width = std::max(i_width, stride_width);
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// Stride width calculated from actual stride value.
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stride_width = std::ceil(std::log2(std::abs(stride)));
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if (i_width + stride_width > max_width) {
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// For (truncated) i*stride to be within the range of dst, the following must hold:
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// i*stride ≡ bitno (mod shift_mod), i.e.
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// i*stride = k*shift_mod + bitno
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//
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// The Diophantine equation on the form ax + by = c:
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// stride*i - shift_mod*k = bitno
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// has solutions iff c is a multiple of d = gcd(a, b), i.e.
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// bitno mod gcd(stride, shift_mod) = 0
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//
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// long long is at least 64 bits in C++11
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long long shift_mod = 1ll << (max_width - case_sign_hint);
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// std::gcd requires C++17
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// bitno_div = std::gcd(stride, shift_mod);
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bitno_div = gcd((long long)stride, shift_mod);
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}
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}
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}
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// long long is at least 64 bits in C++11
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long long max_offset = (1ll << (max_width - case_sign_hint)) - 1;
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long long min_offset = case_sign_hint ? -(1ll << (max_width - 1)) : 0;
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did_something = true;
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newNode = new AstNode(AST_CASE, shift_expr);
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for (int i = 0; i < source_width; i += stride) {
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int start_bit = source_offset + i;
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int end_bit = std::min(start_bit+result_width,source_width) - 1;
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AstNode *cond = new AstNode(AST_COND, mkconst_int(start_bit, true));
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for (int i = 1 - result_width; i < wire_width; i++) {
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// Out of range indexes are handled in genrtlil.cc
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int start_bit = wire_offset + i;
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int end_bit = start_bit + result_width - 1;
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// Check whether the current index can be generated by shift_expr.
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if (start_bit < min_offset || start_bit > max_offset)
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continue;
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if (start_bit%bitno_div != 0 || (stride == 0 && start_bit != 0))
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continue;
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AstNode *cond = new AstNode(AST_COND, mkconst_int(start_bit, case_sign_hint, max_width));
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AstNode *lvalue = children[0]->clone();
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lvalue->delete_children();
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if (member_node)
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@ -2884,19 +2954,17 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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cond->children.push_back(new AstNode(AST_BLOCK, new AstNode(type, lvalue, children[1]->clone())));
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newNode->children.push_back(cond);
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}
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}
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else
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{
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// mask and shift operations, disabled for now
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} else {
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// mask and shift operations
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AstNode *wire_mask = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true)));
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AstNode *wire_mask = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(wire_width-1, true), mkconst_int(0, true)));
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wire_mask->str = stringf("$bitselwrite$mask$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
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wire_mask->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
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wire_mask->is_logic = true;
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while (wire_mask->simplify(true, 1, -1, false)) { }
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current_ast_mod->children.push_back(wire_mask);
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AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true)));
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AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(wire_width-1, true), mkconst_int(0, true)));
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wire_data->str = stringf("$bitselwrite$data$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
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wire_data->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
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wire_data->is_logic = true;
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@ -2952,12 +3020,12 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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shamt = new AstNode(AST_TO_SIGNED, shamt);
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// offset the shift amount by the lower bound of the dimension
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int start_bit = source_offset;
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int start_bit = wire_offset;
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shamt = new AstNode(AST_SUB, shamt, mkconst_int(start_bit, true));
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// reflect the shift amount if the dimension is swapped
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if (children[0]->id2ast->range_swapped)
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shamt = new AstNode(AST_SUB, mkconst_int(source_width - result_width, true), shamt);
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shamt = new AstNode(AST_SUB, mkconst_int(wire_width - result_width, true), shamt);
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// AST_SHIFT uses negative amounts for shifting left
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shamt = new AstNode(AST_NEG, shamt);
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@ -1,6 +1,6 @@
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module gate(
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output reg [`LEFT:`RIGHT] out_u, out_s,
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(* nowrshmsk = `ALT *)
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output reg [`LEFT:`RIGHT] out_u, out_s,
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input wire data,
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input wire [1:0] sel1, sel2
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);
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